公开(公告)号：US20250151292A1

公开(公告)日：2025-05-08

申请号：US18732795

申请日：2024-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changyoung Lee ,  Keonwoo Park ,  Hyunchul Yoon

IPC: H10B80/00 ,  G06F11/10 ,  G11C11/408 ,  G11C11/4091 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes a memory cell array. The memory cell array is connected to a plurality of wordlines and a plurality of bitlines, and includes a plurality of normal memory cells storing normal data and a plurality of error correction code (ECC) memory cells storing ECC data. The second semiconductor layer is disposed with respect to the first semiconductor layer in a vertical direction, and includes a peripheral circuit. The peripheral circuit controls the memory cell array, and includes a row decoder. At least a portion of a region in which the plurality of ECC memory cells are disposed in the first semiconductor layer and at least a portion of a region in which the row decoder is disposed in the second semiconductor layer overlap in a plan view.

公开(公告)号：US11380552B2

公开(公告)日：2022-07-05

申请号：US16858591

申请日：2020-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunchul Yoon ,  Mincheol Kwak ,  Joonghee Kim ,  Jihee Kim ,  Yeongshin Park ,  Jungheun Hwang

IPC: H01L21/308 ,  H01L27/108

Abstract: In order to manufacture an integrated circuit device, a feature layer is formed on a substrate in a first area for forming a plurality of chips and in a second area surrounding the first area. The feature layer has a step difference in the second area. On the feature layer, a hard mask structure including a plurality of hard mask layers stacked on each other is formed. In the first area and the second area, a protective layer covering the hard mask structure is formed. On the protective layer, a photoresist layer is formed. A photoresist pattern is formed by exposing and developing the photoresist layer in the first area by using the step difference in the second area as an alignment key.

公开(公告)号：US20240321940A1

公开(公告)日：2024-09-26

申请号：US18423647

申请日：2024-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungjun Kim ,  Sangwuk Park ,  Hyunchul Yoon ,  Jungpyo Hong

IPC: H01G4/30

CPC classification number: H01L28/60

Abstract: A semiconductor device including a substrate and a capacitor structure arranged on the substrate. The capacitor structure includes a plurality of lower electrodes extending in a vertical direction perpendicular to a surface of the substrate and spaced apart from each other, supporters arranged between the plurality of lower electrodes, an upper electrode spaced apart from each of the plurality of lower electrodes, a dielectric layer arranged between each of the lower electrodes and the upper electrode, and a plurality of particles each in contact with the dielectric layer and arranged between each of the plurality of lower electrodes and the upper electrode.

公开(公告)号：US20230209802A1

公开(公告)日：2023-06-29

申请号：US18088370

申请日：2022-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yuna Lee ,  Sangwuk Park ,  Hyunchul Yoon ,  Seungjae Lee ,  Joonkyu Rhee ,  Chanmin Lee ,  Jungpyo Hong

IPC: H10B12/00

CPC classification number: H10B12/09 ,  H10B12/482 ,  H10B12/50

Abstract: A method of fabricating a semiconductor device includes forming an insulating layer and a peripheral structure on first and second regions of the substrate, forming first and second mask layers on the insulating layer and the peripheral structure, patterning the first and second mask layers to form first and second mask structures on the first and second regions, etching the insulating layer using the first and second mask structures as an etching mask, to form insulating patterns, forming a sacrificial layer in spaces between two adjacent insulating patterns on the first region, removing the second mask pattern on the first region by a dry etching process, forming an anti-oxidation layer on a surface of the second mask layer on the second region after removing the second mask pattern on the first region, and removing the second mask layer with the anti-oxidation layer by a wet etching process.

公开(公告)号：US20210210493A1

公开(公告)日：2021-07-08

申请号：US17028763

申请日：2020-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihee Kim ,  Yeongshin Park ,  Hyunchul Yoon ,  Joonghee Kim ,  Jungheun Hwang

IPC: H01L27/108

Abstract: A semiconductor device includes bit line structures disposed on a substrate, each bit line structure comprising a bit line and an insulating spacer structure, buried contacts which fill lower portions of spaces between bit line structures in the substrate, and landing pads which fill upper portions of the spaces, extend from upper surfaces of the buried contacts to upper surfaces of the bit line structures, and are spaced apart from each other by insulating structures. A first insulating structure is disposed between a first landing pad and a first bit line structure. The first insulating structure includes a sidewall extending along a sidewall of the first landing pad toward the substrate. In a direction extending toward the substrate, the sidewall of the first insulating structure gets closer to a first sidewall of the first bit line structure.

公开(公告)号：US20250169066A1

公开(公告)日：2025-05-22

申请号：US18826334

申请日：2024-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daesun Kim ,  Suklae Kim ,  Cheonbae Kim ,  Youngseok Park ,  Taejin Park ,  Hyunchul Yoon ,  Hyeonkyu Lee ,  Sungsoo Yim ,  Hyungeun Choi

IPC: H10B12/00 ,  G11C11/408 ,  G11C11/4091 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: Provided is a semiconductor device. The semiconductor device includes: a first connection region, a first memory block region, and a second connection region sequentially arranged; a first peripheral circuit region vertically overlapping with the first memory block region; first memory cells in the first memory block region; a first word line extending into the first and second connection regions by crossing the first memory block region, and electrically connected to the first memory cells; a first sub-word line driver in the first peripheral circuit region; and a first word line signal path electrically connecting the first word line and the first sub-word line driver. The first word line signal path includes at least one first routing contact coupled to the first word line in the first connection region, and at least one second routing contact coupled to the first word line in the second connection region.

公开(公告)号：US12238920B2

公开(公告)日：2025-02-25

申请号：US17971256

申请日：2022-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihee Kim ,  Yeongshin Park ,  Hyunchul Yoon ,  Joonghee Kim ,  Jungheun Hwang

IPC: H10B12/00 ,  H01L21/764 ,  H01L21/768 ,  H01L29/66

Abstract: A semiconductor device includes bit line structures disposed on a substrate, each bit line structure comprising a bit line and an insulating spacer structure, buried contacts which fill lower portions of spaces between bit line structures in the substrate, and landing pads which fill upper portions of the spaces, extend from upper surfaces of the buried contacts to upper surfaces of the bit line structures, and are spaced apart from each other by insulating structures. A first insulating structure is disposed between a first landing pad and a first bit line structure. The first insulating structure includes a sidewall extending along a sidewall of the first landing pad toward the substrate. In a direction extending toward the substrate, the sidewall of the first insulating structure gets closer to a first sidewall of the first bit line structure.

公开(公告)号：US20230037972A1

公开(公告)日：2023-02-09

申请号：US17971256

申请日：2022-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihee Kim ,  Yeongshin Park ,  Hyunchul Yoon ,  Joonghee Kim ,  Jungheun Hwang

IPC: H01L27/108 ,  H01L21/768 ,  H01L29/66 ,  H01L21/764

Abstract: A semiconductor device includes bit line structures disposed on a substrate, each bit line structure comprising a bit line and an insulating spacer structure, buried contacts which fill lower portions of spaces between bit line structures in the substrate, and landing pads which fill upper portions of the spaces, extend from upper surfaces of the buried contacts to upper surfaces of the bit line structures, and are spaced apart from each other by insulating structures. A first insulating structure is disposed between a first landing pad and a first bit line structure. The first insulating structure includes a sidewall extending along a sidewall of the first landing pad toward the substrate. In a direction extending toward the substrate, the sidewall of the first insulating structure gets closer to a first sidewall of the first bit line structure.

公开(公告)号：US11508732B2

公开(公告)日：2022-11-22

申请号：US17028763

申请日：2020-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihee Kim ,  Yeongshin Park ,  Hyunchul Yoon ,  Joonghee Kim ,  Jungheun Hwang

IPC: H01L27/108 ,  H01L21/768 ,  H01L29/66 ,  H01L21/764

Abstract: A semiconductor device includes bit line structures disposed on a substrate, each bit line structure comprising a bit line and an insulating spacer structure, buried contacts which fill lower portions of spaces between bit line structures in the substrate, and landing pads which fill upper portions of the spaces, extend from upper surfaces of the buried contacts to upper surfaces of the bit line structures, and are spaced apart from each other by insulating structures. A first insulating structure is disposed between a first landing pad and a first bit line structure. The first insulating structure includes a sidewall extending along a sidewall of the first landing pad toward the substrate. In a direction extending toward the substrate, the sidewall of the first insulating structure gets closer to a first sidewall of the first bit line structure.