公开(公告)号：US20230317849A1

公开(公告)日：2023-10-05

申请号：US17961818

申请日：2022-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Bum KIM ,  Hyo Jin KIM ,  Yong Jun NAM ,  Sang Moon LEE ,  Dong Woo KIM ,  In Geon HWANG

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66545

Abstract: A semiconductor device includes a lower pattern extending in a first direction, and protruding from a substrate in a second direction, a lower insulating pattern on the lower pattern, and in contact with an upper surface of the lower pattern, a channel pattern on the lower insulating pattern, a plurality of gate structures on the lower pattern and spaced apart from each other in the first direction, wherein each of the plurality of gate structures includes a gate electrode and a gate insulating film, and a source/drain pattern disposed on the lower pattern, and connected to the channel pattern. A vertical level of a lowermost portion of the source/drain pattern is lower than a vertical level of a bottom surface of the lower insulating pattern. The gate electrode overlaps the lower insulating pattern in the second direction.