公开(公告)号：US20240145541A1

公开(公告)日：2024-05-02

申请号：US18313630

申请日：2023-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Da Hye KIM ,  Jin Bum KIM ,  Gyeom KIM ,  Young Kwang KIM ,  Kyung Bin CHUN

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes an active pattern including a lower pattern extending in a first direction, and a plurality of sheet patterns spaced apart from the lower pattern in a second direction. The sheet patterns include an uppermost sheet pattern and a plurality of gate structures on the lower pattern and spaced apart from each other in the first direction. Each of the plurality of gate structures includes a gate electrode and a gate insulating film and a source/drain pattern between adjacent ones of the plurality of gate structures. Each of inner gate structures includes a gate electrode and a gate insulating film. A semiconductor liner film includes silicon-germanium, and contacts the gate insulating film of each of the inner gate structures. A portion of the semiconductor liner film protrudes upwardly in the first direction beyond an upper surface of the uppermost sheet pattern.

公开(公告)号：US20180138269A1

公开(公告)日：2018-05-17

申请号：US15715832

申请日：2017-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Hoon KIM ,  Hyun Jung LEE ,  Kyung Hee KIM ,  Sun Jung KIM ,  Jin Bum KIM ,  Il Gyou SHIN ,  Seung Hun LEE ,  Cho Eun LEE ,  Dong Suk SHIN

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/0257 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: There is provided a semiconductor device capable of enhancing short channel effect by forming a carbon-containing semiconductor pattern in a source/drain region. The semiconductor device includes a first gate electrode and a second gate electrode spaced apart from each other on a fin-type pattern, a recess formed in the fin-type pattern between the first gate electrode and the second gate electrode, and a semiconductor pattern including a lower semiconductor film formed along a profile of the recess and an upper semiconductor film on the lower semiconductor film, wherein the lower semiconductor film includes a lower epitaxial layer and an upper epitaxial layer sequentially formed on the fin-type pattern, and a carbon concentration of the upper epitaxial layer is greater than a carbon concentration of the lower epitaxial layer.

公开(公告)号：US20180096845A1

公开(公告)日：2018-04-05

申请号：US15595945

申请日：2017-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cho Eun LEE ,  Jin Bum KIM ,  Kang Hun MOON ,  Jae Myung CHOE ,  Sun Jung KIM ,  Dong Suk SHIN ,  IL GYOU SHIN ,  Jeong Ho YOO

IPC: H01L21/02 ,  H01L21/223 ,  H01L29/66

CPC classification number: H01L21/02661 ,  H01L21/02071 ,  H01L21/223 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a dummy gate electrode on a substrate, forming a trench on a side surface of the dummy gate electrode, performing a bake process of removing an impurity from the trench and forming a source/drain in the trench, wherein the bake process comprises a first stage and a second stage following the first stage, an air pressure in which the substrate is disposed during the first stage is different from an air pressure in which the substrate is disposed during the second stage, and the bake process is performed while the substrate is on a stage rotating the substrate, wherein a revolution per minute (RPM) of the substrate during the first stage is different from a revolution per minute (RPM) of the substrate during the second stage.

公开(公告)号：US20240405113A1

公开(公告)日：2024-12-05

申请号：US18537916

申请日：2023-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yang XU ,  Gyeom KIM ,  Young Kwang KIM ,  Jin Bum KIM ,  Yoon Tae NAM ,  Kyung Bin CHUN ,  Ryong HA ,  Yoon HEO

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a substrate. An active pattern extends in a first horizontal direction on the substrate. First to third nanosheets are sequentially spaced apart from each other in a vertical direction on the active pattern. A gate electrode extends in a second horizontal direction on the active pattern and surrounds the first to third nanosheets. A source/drain region includes a first layer disposed along side walls and a bottom surface of a source/drain trench and a second layer filling the source/drain trench. The second layer includes a first lower side wall facing a side wall of the first nanosheet and an opposite second lower side wall. A lower surface connects the first and second lower side walls and extends in the first horizontal direction. The first and second lower side walls of the second layer extend to have a constant slope in opposite directions to each other.

公开(公告)号：US20240006409A1

公开(公告)日：2024-01-04

申请号：US18138825

申请日：2023-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Woo KIM ,  Jin Bum KIM ,  Sang Moon LEE

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/8234

Abstract: There is provided a semiconductor device including an active pattern which includes a lower pattern extending in a first direction and a plurality of sheet patterns spaced apart from the lower pattern in a second direction on a substrate, the lower pattern including a protruding pattern protruding from the substrate in the second direction, and a capping pattern being in contact with the protruding pattern on the protruding pattern, a first gate structure and a second gate structure which are disposed on the lower pattern and spaced apart from each other in the first direction, and a source/drain pattern which is disposed on the lower pattern and in contact with the sheet pattern, wherein a thickness of the capping pattern in a portion that overlaps the first gate structure is different from a thickness of the capping pattern in a portion that overlaps the second gate structure.

公开(公告)号：US20230317849A1

公开(公告)日：2023-10-05

申请号：US17961818

申请日：2022-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Bum KIM ,  Hyo Jin KIM ,  Yong Jun NAM ,  Sang Moon LEE ,  Dong Woo KIM ,  In Geon HWANG

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66545

Abstract: A semiconductor device includes a lower pattern extending in a first direction, and protruding from a substrate in a second direction, a lower insulating pattern on the lower pattern, and in contact with an upper surface of the lower pattern, a channel pattern on the lower insulating pattern, a plurality of gate structures on the lower pattern and spaced apart from each other in the first direction, wherein each of the plurality of gate structures includes a gate electrode and a gate insulating film, and a source/drain pattern disposed on the lower pattern, and connected to the channel pattern. A vertical level of a lowermost portion of the source/drain pattern is lower than a vertical level of a bottom surface of the lower insulating pattern. The gate electrode overlaps the lower insulating pattern in the second direction.

公开(公告)号：US20210013324A1

公开(公告)日：2021-01-14

申请号：US17038004

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd. ,  Research & Business Foundation Sungkyunkwan University

Inventor： Jin Bum KIM ,  MunHyeon KIM ,  Hyoung Sub KIM ,  Tae Jin PARK ,  Kwan Heum LEE ,  Chang Woo NOH ,  Maria TOLEDANO LU QUE ,  Hong Bae PARK ,  Si Hyung LEE ,  Sung Man WHANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction.

公开(公告)号：US20240421232A1

公开(公告)日：2024-12-19

申请号：US18586125

申请日：2024-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suk YANG ,  Sung-Hwan JANG ,  Do Hee KIM ,  Jin Bum KIM ,  Sung Uk JANG ,  Inhae ZOH

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a lower pattern extending in a first direction, a plurality of wire patterns spaced apart from the lower pattern in a second direction on the lower pattern, and a gate electrode surrounding the plurality of wire patterns and extending in a third direction, on the lower pattern. Each of the plurality of wire patterns includes a transition metal dichalcogenide (TMD) material. Each of the plurality of wire patterns includes a pair of first areas protruding from sidewalls of the gate electrode in the first direction and a second area between the first areas. A phase of the first area is different from a phase of the second area.

公开(公告)号：US20240266288A1

公开(公告)日：2024-08-08

申请号：US18367851

申请日：2023-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Bum KIM

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L23/5286 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: A semiconductor device is provided. The semiconductor device includes: a substrate including a first side and a second side opposite to the first side; an active pattern that is on the first side and extends in a first direction; an etch stop layer that extends along the first side of the substrate and does not extend along side faces of the active pattern; a field insulating film that is on the first side and covers at least a part of the side faces of the active pattern; a gate structure that extends in a second direction intersecting the first direction on the active pattern and the field insulating film; a through contact that extends in a third direction intersecting the first direction and the second direction and penetrates the field insulating film and the etch stop layer; a buried pattern connected to the through contact, inside the substrate; and a backside wiring structure that is on the second side and electrically connected to the buried pattern.

公开(公告)号：US20240153991A1

公开(公告)日：2024-05-09

申请号：US18229218

申请日：2023-08-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyeom KIM ,  Da Hye KIM ,  Young Kwang KIM ,  Jin Bum KIM ,  Kyung Bin CHUN

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes: an active pattern including a lower pattern and a plurality of sheet patterns that are spaced apart from the lower pattern; a gate structure disposed on the lower pattern; and a source/drain pattern disposed on the lower pattern, and connected to each of the plurality of sheet patterns, wherein the plurality of sheet patterns include a first sheet pattern and a second sheet pattern. The second sheet pattern is disposed between the first sheet pattern and the lower pattern. A first upper width of an upper surface of the first sheet pattern is greater than a first lower width of a bottom surface of the first sheet pattern, and a second upper width of an upper surface of the second sheet pattern is smaller than a second lower width of a bottom surface of the second sheet pattern.