公开(公告)号：US20170222006A1

公开(公告)日：2017-08-03

申请号：US15298746

申请日：2016-10-20

申请人： Samsung Electronics Co., Ltd.

发明人： Dong Chan SUH ,  Yong Suk TAK ,  Gi Gwan PARK ,  Mi Seon PARK ,  Moon Seung YANG ,  Seung Hun LEE ,  Poren TANG

IPC分类号： H01L29/423 ,  H01L29/78 ,  H01L23/528

CPC分类号： H01L29/42376 ,  H01L23/5283 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/66439 ,  H01L29/7831

摘要： A semiconductor device includes at least a first wire pattern, a gate electrode, a semiconductor pattern, a gate insulating layer, and a first spacer. The first wire pattern is on a substrate and isolated from the substrate. The gate electrode surrounds and intersects the first wire pattern. The semiconductor pattern is on both sides of the first wire pattern, and the semiconductor pattern includes a portion which overlaps the first wire pattern. The gate insulating layer is disposed between the gate electrode and the first wire pattern, and the gate insulating layer surrounds the first wire pattern. The first spacer is between the first wire pattern and the substrate, and the first spacer is between the gate insulating layer and the semiconductor pattern

公开(公告)号：US20190006485A1

公开(公告)日：2019-01-03

申请号：US15865531

申请日：2018-01-09

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Tea Won KIM ,  Yong Suk TAK ,  Ki Yeon PARK

IPC分类号： H01L29/66

CPC分类号： H01L29/6656 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795

摘要： A method for fabricating a semiconductor device includes forming a stacked structure including at least one sacrificial layer and at least one semiconductor layer alternately stacked on a substrate, forming a dummy gate structure on the stacked structure, etching a recess in the stacked structure using the dummy gate structure as a mask, etching portions of the sacrificial layer exposed by the recess to form an etched sacrificial layer, forming a first spacer film on the etched sacrificial layer, forming a second spacer film on the first spacer film, the second spacer film including a material different from a material of the first spacer film, removing a first portion of the second spacer film, such that a second portion of the second spacer film remains, and forming a third spacer film on the second portion of the second spacer film.

公开(公告)号：US20230137072A1

公开(公告)日：2023-05-04

申请号：US17849086

申请日：2022-06-24

申请人： Samsung Electronics Co., Ltd.

发明人： Teawon KIM ,  Yurim KIM ,  Seohee PARK ,  Kong-Soo LEE ,  Yong Suk TAK

IPC分类号： H01L29/06 ,  H01L29/786 ,  H01L29/78

摘要： A semiconductor device includes a channel layer disposed on a substrate and a gate structure formed on or under the channel layer. The channel layer includes a single-layer oxide semiconductor material, the channel layer includes indium (In), gallium (Ga), and oxygen (O), the channel layer includes a first region, a second region, and a third region, the third region contacting the gate structure, a second region between the first region and the third region, the first region is the closer to the substrate than the second region and the third region, each of the first region and the third region has a concentration of Ga higher than a concentration of In, and the second region has a concentration of In higher than a concentration of Ga.

公开(公告)号：US20230134099A1

公开(公告)日：2023-05-04

申请号：US17825441

申请日：2022-05-26

申请人： Samsung Electronics Co., Ltd.

发明人： Teawon KIM ,  Yurim KIM ,  Seohee PARK ,  Kong-Soo LEE ,  Yong Suk TAK

IPC分类号： H01L27/108

摘要： A semiconductor device includes: a substrate; a conductive line extending on the substrate in a first horizontal direction; an isolation insulating layer extending on the substrate and the conductive line in a second horizontal direction intersecting with the first horizontal direction, and defining a channel trench extending through the isolation insulating layer from an upper surface of the isolation insulating layer to a lower surface of the isolation insulating layer; a crystalline oxide semiconductor layer extending along at least a portion of an inner side surface of the channel trench and at least a portion of a bottom surface of the channel trench and coming in contact with the conductive line; and a gate electrode extending on the crystalline oxide semiconductor layer inside the channel trench in the second horizontal direction.