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公开(公告)号：US20230352297A1
公开(公告)日：2023-11-02
申请号：US18183571
申请日：2023-03-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yurim KIM , Teawon Kim , Seunghee Lee , Seungwoo Jang , Yongsuk Tak
IPC: H01L21/02
CPC classification number: H01L21/02194 , H01L21/02205
Abstract: A method of manufacturing a semiconductor device including providing a first precursor on a substrate to adsorb a first element of the first precursor onto a first region of the substrate, providing a second precursor on the substrate to adsorb a second element of the second precursor onto a second region of the substrate, the second region being different from the first region, and providing a reactant including oxygen on the substrate to form an oxide semiconductor layer including the first element of the first precursor, the second element of the second precursor, and the oxygen of the reactant may be provided.
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公开(公告)号：US20230255017A1
公开(公告)日：2023-08-10
申请号：US18103596
申请日：2023-01-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Teawon KIM , Jiwon YUN , Yurim KIM , Junghan LEE , Yongsuk TAK
IPC: H10B12/00
CPC classification number: H10B12/315 , H10B12/482 , H10B12/05 , H10B12/0335
Abstract: A semiconductor apparatus includes a bit line extending in a first horizontal direction on a substrate; a channel layer on the bit line, the channel layer extending in a vertical direction, including a first oxide semiconductor material that includes indium, and having a first side wall and a second side wall; a word line on the first side wall of the channel layer; a contact forming region on a top surface and an upper portion of the second side wall of the channel layer, the contact forming region including a second oxide semiconductor material that includes indium and having a resistivity lower than a resistivity of the channel layer; a contact layer on the contact forming region; and a capacitor structure on a top surface of the contact layer.
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公开(公告)号：US20250107065A1
公开(公告)日：2025-03-27
申请号：US18619490
申请日：2024-03-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jin-Seong PARK , Jihyun KHO , Seunghee LEE , Yurim KIM , Yong-Suk TAK , Dong-Gyu KIM
IPC: H10B12/00
Abstract: A semiconductor device includes a semiconductor pattern, a dielectric layer on the semiconductor pattern, and a conductive pattern on the dielectric layer. Each of the semiconductor pattern and the dielectric layer includes impurities. The dielectric layer includes a concentration profile of impurities including a first variation section including a first concentration of impurities decreasing throughout the dielectric layer toward the semiconductor pattern, and a second variation section including a second concentration of impurities decreasing throughout the dielectric layer toward the semiconductor pattern.
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Patent Agency Ranking
公开(公告)号：US20240224510A1
公开(公告)日：2024-07-04
申请号：US18354041
申请日：2023-07-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seunghee LEE , Jaekyeong JEONG , Seungwan SEO , Yongsuk TAK , Yurim KIM , Teawon KIM , Joohee JEONG
IPC: H10B12/00
CPC classification number: H10B12/485 , H10B12/315 , H10B12/34
Abstract: A field-effect transistor includes an insulating barrier layer on a substrate, a gate electrode extending on the insulating barrier layer, a gate insulating layer covering opposite side surfaces and a top surface of the gate electrode, an oxide semiconductor layer on the gate insulating layer and including at least one metal element selected from indium (In) and zinc (Zn), and a source structure and a drain structure separated from each other, the source structure and the drain structure electrically connected to the oxide semiconductor layer. Each of the source structure and the drain structure includes an indium gallium tin oxide (IGTO) film on the oxide semiconductor layer, a conductive metal nitride film on the IGTO film, one of a source electrode and a drain electrode on the conductive metal nitride film, and a top capping layer on a top surface of one of the source electrode and the drain electrode.
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公开(公告)号：US20230354605A1
公开(公告)日：2023-11-02
申请号：US18175198
申请日：2023-02-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Teawon KIM , Yurim KIM , Seunghee LEE , Seungwoo JANG , Yong-Suk TAK
Abstract: A semiconductor memory device includes a bit line, a channel pattern including a horizontal channel portion on the bit line and a vertical channel portion vertically protruding from the horizontal channel portion, a word line on the horizontal channel portion and on a sidewall of the vertical channel portion, and a gate insulating pattern between the word line and the channel pattern. The channel pattern includes an oxide semiconductor and includes first, second, and third channel layers sequentially stacked. The first to third channel layers include a first metal, and the second channel layer further includes a second metal different from the first metal. At least a portion of the first channel layer contacts the bit line.
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公开(公告)号：US20230137072A1
公开(公告)日：2023-05-04
申请号：US17849086
申请日：2022-06-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Teawon KIM , Yurim KIM , Seohee PARK , Kong-Soo LEE , Yong Suk TAK
IPC: H01L29/06 , H01L29/786 , H01L29/78
Abstract: A semiconductor device includes a channel layer disposed on a substrate and a gate structure formed on or under the channel layer. The channel layer includes a single-layer oxide semiconductor material, the channel layer includes indium (In), gallium (Ga), and oxygen (O), the channel layer includes a first region, a second region, and a third region, the third region contacting the gate structure, a second region between the first region and the third region, the first region is the closer to the substrate than the second region and the third region, each of the first region and the third region has a concentration of Ga higher than a concentration of In, and the second region has a concentration of In higher than a concentration of Ga.
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公开(公告)号：US20230134099A1
公开(公告)日：2023-05-04
申请号：US17825441
申请日：2022-05-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Teawon KIM , Yurim KIM , Seohee PARK , Kong-Soo LEE , Yong Suk TAK
IPC: H01L27/108
Abstract: A semiconductor device includes: a substrate; a conductive line extending on the substrate in a first horizontal direction; an isolation insulating layer extending on the substrate and the conductive line in a second horizontal direction intersecting with the first horizontal direction, and defining a channel trench extending through the isolation insulating layer from an upper surface of the isolation insulating layer to a lower surface of the isolation insulating layer; a crystalline oxide semiconductor layer extending along at least a portion of an inner side surface of the channel trench and at least a portion of a bottom surface of the channel trench and coming in contact with the conductive line; and a gate electrode extending on the crystalline oxide semiconductor layer inside the channel trench in the second horizontal direction.
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公开(公告)号：US20230052762A1
公开(公告)日：2023-02-16
申请号：US17697423
申请日：2022-03-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Teawon KIM , Hyung Joon KIM , Yong-Suk TAK , Yurim KIM , Kongsoo LEE
IPC: H01L29/786 , H01L27/12 , H01L29/423
Abstract: Disclosed is a semiconductor device comprising an oxide semiconductor layer on a substrate and including a first part and a pair of second parts that are spaced apart from each other across the first part, a gate electrode on the first part of the oxide semiconductor layer, and a pair of electrodes on corresponding second parts of the oxide semiconductor layer. A first thickness of the first part of the oxide semiconductor layer is less than a second thickness of each second part of the oxide semiconductor layer. A number of oxygen vacancies in the first part of the oxide semiconductor layer is less than a number of oxygen vacancies in each second part of the oxide semiconductor layer.
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