公开(公告)号：US20230170303A1

公开(公告)日：2023-06-01

申请号：US18153028

申请日：2023-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyeok SON ,  Junwoo LEE ,  Sungdong CHO

IPC: H01L23/535 ,  H01L21/768 ,  H10B12/00

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/76843 ,  H10B12/09 ,  H10B12/34 ,  H10B12/50 ,  H10B12/053 ,  H10B12/315 ,  H10B12/0335 ,  H10B12/482 ,  H10B12/485

Abstract: A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material.

公开(公告)号：US20250070022A1

公开(公告)日：2025-02-27

申请号：US18634325

申请日：2024-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyun LEE ,  Hyejin KIM ,  Yonghyeok SON ,  Jichang SIM ,  Joo-Sung LEE ,  Yujin CHO

IPC: H01L23/528 ,  H01L23/522 ,  H10B12/00

Abstract: A semiconductor device may include a substrate including a cell array region, a core region, and a peripheral circuit region, a core circuit wiring on the core region of the substrate, a core signal wiring overlapping the core circuit wiring, and a contact plug between the core circuit wiring and the core signal wiring. The contact plug may connect the core circuit wiring to the core signal wiring. A positional relationship between the core signal wiring and the contact plug may be different depending on distance from the peripheral circuit region.

公开(公告)号：US20250096141A1

公开(公告)日：2025-03-20

申请号：US18961767

申请日：2024-11-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyeok SON ,  Junwoo LEE ,  Sungdong CHO

IPC: H01L23/535 ,  H01L21/768 ,  H10B12/00

Abstract: A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material.

公开(公告)号：US20220139836A1

公开(公告)日：2022-05-05

申请号：US17330795

申请日：2021-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyeok SON ,  Junwoo LEE ,  Sungdong CHO

IPC: H01L23/535 ,  H01L27/108 ,  H01L21/768

Abstract: A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material.