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公开(公告)号：US20170070980A1
公开(公告)日：2017-03-09
申请号：US15228512
申请日：2016-08-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yoochang EUN , Mingoo KIM , Chaehag YI
CPC classification number: H04L5/0092 , H04L1/0046 , H04L1/0053 , H04L1/0072 , H04L5/0053
Abstract: A method and an apparatus are provided for determining a downlink control indicator (DCI) at a receiver. A signal is received at the receiver. The receiver measures channel quality based on the received signal. Signals of physical downlink control channel (PDCCH) areas that correspond to each channel format indicator (CFI) in the received signal are decoded, if a measurement of the channel quality is not a configuration condition. The receiver obtains the CFI by decoding a physical control format indicator channel (PCFICH) of the received signal, if the measurement of the channel quality is the configuration condition. The receiver determines the DCI based on the decoded signals.
Abstract translation: 提供了一种用于在接收机处确定下行链路控制指示符（DCI）的方法和装置。 在接收机处接收信号。 接收机根据接收到的信号测量信道质量。 如果信道质量的测量不是配置条件，则对与接收信号中的每个信道格式指示符（CFI）相对应的物理下行链路控制信道（PDCCH）区域的信号进行解码。 如果信道质量的测量是配置条件，则接收器通过解码接收信号的物理控制格式指示符信道（PCFICH）来获得CFI。 接收机基于解码的信号确定DCI。
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Patent Agency Ranking
公开(公告)号：US20230170921A1
公开(公告)日：2023-06-01
申请号：US18058388
申请日：2022-11-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yoochang EUN , Woongjae HAN
IPC: H03M13/11
CPC classification number: H03M13/1131 , H03M13/1148
Abstract: There is provided a decoding apparatus for decoding a low density parity check (LDPC) code, wherein the decoding apparatus includes a memory a memory configured to store a scheduling table indicating a desired processing order of a plurality of rows included in a parity check matrix and a plurality of columns included in each of the rows of the parity check matrix, and processing circuitry configured to decode the LDPC code based on the scheduling table, the decoding including performing processing on at least one column included in a second scheduled row of the parity check matrix before processing of all columns included in a first scheduled row of the parity check matrix has been completed.
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公开(公告)号：US20180026662A1
公开(公告)日：2018-01-25
申请号：US15339264
申请日：2016-10-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyungu KANG , Yoochang EUN
CPC classification number: H03M13/413 , H03M13/23 , H03M13/3738 , H03M13/3961 , H03M13/4107 , H03M13/6502 , H03M13/658 , H03M13/6583 , H04L1/0045 , H04L1/0046 , H04L1/0052 , H04L1/0059 , H04W72/042 , H04W84/042
Abstract: A mobile device includes a display, a mobile-communication modem including a Viterbi decoder (VD) configured to decode a tail biting convolutional code (TBCC)-encoded data, a memory coupled to the mobile-communication modem, and a wireless antenna coupled to the mobile-communication modem and to receive a Physical Downlink Control Channel (PDCCH). The VD is configured to: receive data encoded by TBCC; select a candidate to initiate a training section; determine final path metric (PM) values of possible states at a last step of the training section; determine a PM-related value based on the final PM values of the possible states; and determine an early termination of a decoding for the candidate based on the PM-related value.
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公开(公告)号：US20180013447A1
公开(公告)日：2018-01-11
申请号：US15340992
申请日：2016-11-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyungu KANG , Yoochang EUN
CPC classification number: H03M13/23 , H03M13/4107 , H03M13/413 , H03M13/4169 , H04L1/0045 , H04L1/0059
Abstract: A convolutional decoder includes a first storage, a second storage, a branch metric processor to determine branch metrics for transitions of states from a start step to a last step according to input bit streams, an ACS processor to select maximum likelihood path metrics to determine a survival path according to the branch metrics and to update states of the start step to the first storage and the second storage alternately based on the selection of the maximum likelihood path metrics, and a trace back logic to selectively trace back the survival path based on the states of the start step stored in a selected storage among the first storage and the second storage.
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公开(公告)号：US20250119161A1
公开(公告)日：2025-04-10
申请号：US18982129
申请日：2024-12-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yoochang EUN , Woongjae HAN
Abstract: There is provided a decoding apparatus for decoding a low density parity check (LDPC) code, wherein the decoding apparatus includes a memory a memory configured to store a scheduling table indicating a desired processing order of a plurality of rows included in a parity check matrix and a plurality of columns included in each of the rows of the parity check matrix, and processing circuitry configured to decode the LDPC code based on the scheduling table, the decoding including performing processing on at least one column included in a second scheduled row of the parity check matrix before processing of all columns included in a first scheduled row of the parity check matrix has been completed.
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公开(公告)号：US20180351580A1
公开(公告)日：2018-12-06
申请号：US16057719
申请日：2018-08-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyungu KANG , Yoochang EUN
CPC classification number: H03M13/23 , H03M13/4107 , H03M13/413 , H03M13/4169 , H04L1/0045 , H04L1/0059
Abstract: A convolutional decoder includes a first storage, a second storage, a branch metric processor to determine branch metrics for transitions of states from a start step to a last step according to input bit streams, an ACS processor to select maximum likelihood path metrics to determine a survival path according to the branch metrics and to update states of the start step to the first storage and the second storage alternately based on the selection of the maximum likelihood path metrics, and a trace back logic to selectively trace back the survival path based on the states of the start step stored in a selected storage among the first storage and the second storage.
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