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    Page buffer circuit and memory device including the same
    1.
    发明授权
    Page buffer circuit and memory device including the same 有权

    公开(公告)号：US12073909B2

    公开(公告)日：2024-08-27

    申请号：US18085963

    申请日：2022-12-21

    申请人： Samsung Electronics Co., Ltd.

    发明人： Yongsung Cho ,  Jinwoo Park ,  Hyunjun Yoon ,  Yoonhee Choi

    IPC分类号： G11C16/06 ,  G11C7/06 ,  G11C7/10 ,  G11C16/34

    CPC分类号： G11C7/065 ,  G11C7/1039 ,  G11C7/1057 ,  G11C7/1084 ,  G11C16/3404

    摘要： A memory device includes a memory cell array, a page buffer circuit, and a counting circuit. The page buffer circuit includes a first and second page buffer columns connected to the memory cell array. The first page buffer column includes a first page buffer unit and the second page buffer column includes a second page buffer unit in a first stage. The first page buffer unit performs a first sensing operation in response to a first sensing signal, and the second page buffer unit performs a second sensing operation in response to a second sensing signal. The counting circuit counts a first number of memory cells included in a first threshold voltage region from a result of the first sensing operation, and counts a second number of memory cells included in a second threshold voltage region from a result of the second sensing operation.

    CLOTHING MANAGEMENT APPARATUS AND METHOD FOR CONTROLLING THEREOF
    2.
    发明申请
    CLOTHING MANAGEMENT APPARATUS AND METHOD FOR CONTROLLING THEREOF 审中-公开

    公开(公告)号：US20200208319A1

    公开(公告)日：2020-07-02

    申请号：US16719227

    申请日：2019-12-18

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Jungmin Lee ,  Minjeong Kang ,  Yoonhee Choi

    IPC分类号： D06F33/00 ,  D06F34/18 ,  D06F34/28

    摘要： A clothing management apparatus may include a display and a processor to, based on a state of a garment in an image of the garment, determine a management necessity of the garment, based on the management necessity, determine a management completeness that is expected when the garment is managed according to a management mode among a plurality of management modes, based on the management completeness, generate an expected image of the garment when the garment is managed according to the management mode, and control the display to display the expected image to a user.

    PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME
    4.
    发明申请
    PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20220068322A1

    公开(公告)日：2022-03-03

    申请号：US17222024

    申请日：2021-04-05

    申请人： Samsung Electronics Co., Ltd.

    发明人： Yongsung Cho ,  Jinwoo Park ,  Hyunjun Yoon ,  Yoonhee Choi

    IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C16/34

    摘要： A memory device includes a memory cell array, a page buffer circuit, and a counting circuit. The page buffer circuit includes a first and second page buffer columns connected to the memory cell array. The first page buffer column includes a first page buffer unit and the second page buffer column includes a second page buffer unit in a first stage. The first page buffer unit performs a first sensing operation in response to a first sensing signal, and the second page buffer unit performs a second sensing operation in response to a second sensing signal. The counting circuit counts a first number of memory cells included in a first threshold voltage region from a result of the first sensing operation, and counts a second number of memory cells included in a second threshold voltage region from a result of the second sensing operation.

    PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME
    7.
    发明申请
    PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20230131700A1

    公开(公告)日：2023-04-27

    申请号：US18085963

    申请日：2022-12-21

    申请人： Samsung Electronics Co., Ltd.

    发明人： Yongsung Cho ,  Jinwoo Park ,  Hyunjun Yoon ,  Yoonhee Choi

    IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C16/34

    摘要： A memory device includes a memory cell array, a page buffer circuit, and a counting circuit. The page buffer circuit includes a first and second page buffer columns connected to the memory cell array. The first page buffer column includes a first page buffer unit and the second page buffer column includes a second page buffer unit in a first stage. The first page buffer unit performs a first sensing operation in response to a first sensing signal, and the second page buffer unit performs a second sensing operation in response to a second sensing signal. The counting circuit counts a first number of memory cells included in a first threshold voltage region from a result of the first sensing operation, and counts a second number of memory cells included in a second threshold voltage region from a result of the second sensing operation.