公开(公告)号：US09384092B2

公开(公告)日：2016-07-05

申请号：US14300289

申请日：2014-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae Hyun Kim ,  Seung Jun Bae ,  Young Soo Sohn ,  Tae Young Oh ,  Won Jin Lee

IPC: G11C29/42 ,  G06F11/10 ,  G11C7/08 ,  G11C7/06 ,  G11C29/54 ,  G11C11/4091 ,  G11C11/419

CPC classification number: G06F11/1076 ,  G06F11/1048 ,  G11C7/065 ,  G11C7/08 ,  G11C11/4091 ,  G11C11/419

Abstract: A semiconductor memory device includes; a memory cell array comprising a first sub-memory cell array storing first data having a first characteristic and a second sub-memory cell array storing second data having a second characteristic different from the first characteristic, a first peripheral circuit operatively associated with only the first sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the first sub-memory cell array, and a second peripheral circuit operatively associated with only the second sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the second sub-memory cell array.

Abstract translation: 半导体存储器件包括： 存储单元阵列，包括存储具有第一特性的第一数据的第一子存储单元阵列和存储具有与第一特性不同的第二特性的第二数据的第二子存储单元阵列;第一外围电路， 子存储器单元阵列，以执行指向第一子存储单元阵列的目标存储单元的读取操作和写入操作中的至少一个，以及仅与第二子存储单元阵列可操作地相关联的第二外围电路， 执行指向第二子存储单元阵列的目标存储单元的读取操作和写入操作中的至少一个。

公开(公告)号：US09305631B1

公开(公告)日：2016-04-05

申请号：US14107669

申请日：2013-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Soo Sohn ,  Jong Pil Son ,  Jae Sung Kim ,  Chul Woo Park

IPC: G06F12/10 ,  G11C11/406 ,  G11C11/402

CPC classification number: G11C11/40607 ,  G06F12/1018 ,  G11C7/00 ,  G11C11/402 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/408

Abstract: Provided is a profiling unit and method for profiling a number of times that an input/output address of a semiconductor device is accessed. The profiling unit includes a hash unit configured to produce at least one hash value by perform a hash operation on the input/output address, and a profiling circuit configured to profile the number of times that the input/output address is accessed by using the at least one hash value.

Abstract translation: 提供了一种用于轮廓访问半导体器件的输入/输出地址的次数的分析单元和方法。 简档单元包括散列单元，其被配置为通过对输入/输出地址执行散列操作来产生至少一个散列值;以及简档电路，其被配置为通过使用at来描述输入/输出地址被访问的次数 最少一个哈希值。