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    Memory device for reducing a write fail, a system including the same, and a method thereof
    3.
    发明授权
    Memory device for reducing a write fail, a system including the same, and a method thereof 有权
    用于减少写入失败的存储器件，包括其的系统及其方法

    公开(公告)号：US09335951B2

    公开(公告)日：2016-05-10

    申请号：US14013275

    申请日：2013-08-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jong Pil Son ,  Chul Woo Park ,  Hak Soo Yu ,  Hong Sun Hwang

    IPC: G06F3/00 ,  G06F3/06 ,  G11C7/00 ,  G11C11/4076 ,  G06F13/16

    CPC classification number: G06F3/061 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0676 ,  G06F3/068 ,  G06F13/1642 ,  G11C7/00 ,  G11C7/1048 ,  G11C11/4076 ,  Y02D10/14

    Abstract: A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller is configured to continuously perform a plurality of write commands on the memory device between an active command and a precharge command. In the memory system, when after a first write operation having a last write command of the plurality of write commands is performed and then the precharge command is issued, the last write command is issued for a second write operation after the precharge command. The first write operation and the second write operation write a same data to memory cells of plurality of memory cells having a same address.

    Abstract translation: 存储器系统包括存储器件和存储器控制器。 存储装置包括多个存储单元。 存储器控制器被配置为在活动命令和预充电命令之间在存储器设备上连续地执行多个写入命令。 在存储器系统中，当执行了具有多个写入命令的最后写入命令的第一次写入操作之后，然后执行预充电命令时，在预充电命令之后发出最后一个写入命令用于第二次写入操作。 第一写入操作和第二写入操作将相同的数据写入具有相同地址的多个存储单元的存储单元。

    SEMICONDUCTOR MEMORY AND MEMORY SYSTEM INCLUDING THE SEMICONDUCTOR MEMORY
    10.
    发明申请
    SEMICONDUCTOR MEMORY AND MEMORY SYSTEM INCLUDING THE SEMICONDUCTOR MEMORY 有权
    半导体存储器和存储器系统，包括半导体存储器

    公开(公告)号：US20140241099A1

    公开(公告)日：2014-08-28

    申请号：US14100387

    申请日：2013-12-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seong-Young Seo ,  Chul Woo Park

    IPC: G11C8/12

    CPC classification number: G11C8/12 ,  G11C5/04 ,  G11C8/06

    Abstract: A memory system is provided which includes multiple semiconductor memories having arrays of memory cells and a memory controller configured to provide an address in common to the multiple memories. First and second addresses corresponding to first and second rows of memory cells in first and second memories are selected according to the address in common. The first row and its adjacent rows in the first memory can all be different from the second row and its adjacent rows in the second semiconductor memory. Different conversion schemes can provide scramble information used to convert the address in common into the first and second addresses.

    Abstract translation: 提供了一种存储器系统，其包括具有存储器单元阵列的多个半导体存储器和被配置为向多个存储器提供公共地址的存储器控​​制器。 根据共同的地址选择与第一和第二存储器中的第一和第二行存储单元对应的第一和第二地址。 第一存储器中的第一行及其相邻行全部可以不同于第二半导体存储器中的第二行及其相邻行。 不同的转换方案可以提供用于将共同地址转换成第一和第二地址的加扰信息。

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