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公开(公告)号：US09449650B2
公开(公告)日：2016-09-20
申请号：US14317099
申请日：2014-06-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong-hyun Seok , Do-hyung Kim , Won-hyung Song , Young-ho Lee
CPC classification number: G11C5/04 , G11C7/02 , G11C7/10 , G11C2207/105
Abstract: A memory module that includes: a printed circuit board having a connecting terminal; memory chips arranged on the printed circuit board; data buffers disposed on a first surface of the printed circuit board and corresponding to the memory chips; and resistance units disposed on a second surface of the printed circuit board and corresponding to the data buffers.
Abstract translation: 一种存储模块，包括：具有连接端子的印刷电路板; 存储芯片布置在印刷电路板上; 数据缓冲器，布置在印刷电路板的第一表面上并对应于存储器芯片; 和布置在印刷电路板的第二表面上并对应于数据缓冲器的电阻单元。
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公开(公告)号：US20200065289A1
公开(公告)日：2020-02-27
申请号：US16671601
申请日：2019-11-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sun-young Lim , Hui-chong Shin , ln-su Choi , Young-ho Lee
Abstract: A memory system configured to support internal data (DQ) termination of a data buffer is provided. The memory system includes a first memory module, which is a target memory module accessed by an external device, and a second memory module, which is a non-target memory module not accessed by the external device. The second memory module performs the internal DQ termination on an internal data path during an internal operation mode in which data communication is performed by using the internal data path between internal memory chips. Signal reflection over the internal data path is reduced or prohibited due to the internal DQ termination, and thus, signal integrity is improved.
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Patent Agency Ranking
公开(公告)号：US20180329850A1
公开(公告)日：2018-11-15
申请号：US15916929
申请日：2018-03-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sun-young Lim , Hui-chong Shin , In-su Choi , Young-ho Lee
CPC classification number: G06F13/4086 , G06F3/0614 , G06F3/0656 , G06F3/0659 , G06F12/0246
Abstract: A memory system configured to support internal data (DQ) termination of a data buffer is provided. The memory system includes a first memory module, which is a target memory module accessed by an external device, and a second memory module, which is a non-target memory module not accessed by the external device. The second memory module performs the internal DQ termination on an internal data path during an internal operation mode in which data communication is performed by using the internal data path between internal memory chips. Signal reflection over the internal data path is reduced or prohibited due to the internal DQ termination, and thus, signal integrity is improved.
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公开(公告)号：US10978170B2
公开(公告)日：2021-04-13
申请号：US16124379
申请日：2018-09-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Young-ho Lee , Sung-joo Park , Young Yun , Yong-jin Kim , Jae-jun Lee
IPC: G11C29/00 , G11C29/38 , G11C29/36 , G11C11/409 , G11C7/10 , G01K7/01 , H05K1/11 , H05K1/18 , G11C5/04
Abstract: A memory device including: a loopback circuit for performing a loopback operation, wherein the loopback operation includes receiving, via a loopback channel, test signals provided from a test device and feeding back the test signals to the test device via the loopback channel; and an information management circuit for outputting information of the memory device to the loopback channel.
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公开(公告)号：US10684979B2
公开(公告)日：2020-06-16
申请号：US16671601
申请日：2019-11-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sun-young Lim , Hui-chong Shin , In-su Choi , Young-ho Lee
Abstract: A memory system configured to support internal data (DQ) termination of a data buffer is provided. The memory system includes a first memory module, which is a target memory module accessed by an external device, and a second memory module, which is a non-target memory module not accessed by the external device. The second memory module performs the internal DQ termination on an internal data path during an internal operation mode in which data communication is performed by using the internal data path between internal memory chips. Signal reflection over the internal data path is reduced or prohibited due to the internal DQ termination, and thus, signal integrity is improved.
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公开(公告)号：US20190237152A1
公开(公告)日：2019-08-01
申请号：US16124379
申请日：2018-09-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Young-ho Lee , Sung-joo Park , Young Yun , Yong-jin Kim , Jae-jun Lee
IPC: G11C29/38 , G11C29/36 , G11C11/409
CPC classification number: G11C29/38 , G01K7/01 , G11C11/409 , G11C29/36 , H05K1/117 , H05K1/181 , H05K2201/10151 , H05K2201/10159 , H05K2201/10522
Abstract: A memory device including: a loopback circuit for performing a loopback operation, wherein the loopback operation comprises receiving, via a loopback channel, test signals provided from a test device and feeding back the test signals to the test device via the loopback channel; and an information management circuit for outputting information of the memory device to the loopback channel.
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公开(公告)号：US20150016047A1
公开(公告)日：2015-01-15
申请号：US14317099
申请日：2014-06-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong-hyun Seok , Do-hyung Kim , Won-hyung Song , Young-ho Lee
IPC: G06F1/18
CPC classification number: G11C5/04 , G11C7/02 , G11C7/10 , G11C2207/105
Abstract: A memory module that includes: a printed circuit board having a connecting terminal; memory chips arranged on the printed circuit board; data buffers disposed on a first surface of the printed circuit board and corresponding to the memory chips; and resistance units disposed on a second surface of the printed circuit board and corresponding to the data buffers.
Abstract translation: 一种存储模块，包括：具有连接端子的印刷电路板; 存储芯片布置在印刷电路板上; 数据缓冲器，布置在印刷电路板的第一表面上并对应于存储器芯片; 和布置在印刷电路板的第二表面上并对应于数据缓冲器的电阻单元。
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