公开(公告)号：US20180102347A1

公开(公告)日：2018-04-12

申请号：US15840314

申请日：2017-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-seop SHIM ,  Jaehong Kim

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  G11C5/04 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/30 ,  G11C29/021 ,  H01L23/49838 ,  H01L23/528 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/1438 ,  H01L2924/15311

Abstract: Disclosed is a data storage device including a controller and a multi-stack chip package, and a method of operating a data storage device. The multi-stack chip package includes a first semiconductor chip arranged on a package substrate, a second semiconductor chip arranged on the first semiconductor chip, and a third semiconductor chip is arranged between the first and second semiconductor chips. The controller can control the first to third semiconductor chips by using a feature parameter measured from each semiconductor chip and a target value that may be originally designed by a memory vendor.

公开(公告)号：US20170330860A1

公开(公告)日：2017-11-16

申请号：US15443963

申请日：2017-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-seop SHIM ,  JAEHONG KIM

IPC: H01L25/065 ,  G11C16/08 ,  G11C16/10 ,  H01L23/498 ,  H01L23/528 ,  G11C16/04 ,  G11C16/30 ,  H01L23/00

CPC classification number: H01L25/0657 ,  G11C5/04 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/30 ,  G11C29/021 ,  H01L23/49838 ,  H01L23/528 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/1438 ,  H01L2924/15311

Abstract: Disclosed is a data storage device including a controller and a multi-stack chip package, and a method of operating a data storage device. The multi-stack chip package includes a first semiconductor chip arranged on a package substrate, a second semiconductor chip arranged on the first semiconductor chip, and a third semiconductor chip is arranged between the first and second semiconductor chips. The controller can control the first to third semiconductor chips by using a feature parameter measured from each semiconductor chip and a target value that may be originally designed by a memory vendor.