公开(公告)号：US20150117083A1

公开(公告)日：2015-04-30

申请号：US14590717

申请日：2015-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-pil SON ,  Young-soo SOHN

IPC: G11C29/44 ,  G11C17/16

CPC classification number: G11C29/44 ,  G11C8/00 ,  G11C11/4087 ,  G11C16/08 ,  G11C17/16 ,  G11C29/04 ,  G11C29/787 ,  G11C29/808 ,  G11C2029/4402

Abstract: A memory device including: a memory cell array including normal memory cells and spare memory cells arranged in rows and columns including normal columns including the normal memory cells and at least one spare column including spare memory cells, a segment match determining circuit configured to compare a segment address with row address information corresponding to a failed segment and to generate a load control signal, and a column match determining circuit configured to compare column address information corresponding to a failed column in response to the load control signal with a column address and to generate a column address replacement control signal, wherein the memory cells connected to fail columns of the fail segment are replaced with memory cells connected to columns of the spare memory cells in response to the column address replacement control signal.

Abstract translation: 一种存储器件，包括：存储单元阵列，包括正常存储单元和排列成行和列的备用存储单元，所述备用存储单元包括包括常规存储单元的常规列和至少一个备用存储单元的备用列，段匹配确定电路， 段地址，其中行地址信息对应于故障段并产生负载控制信号;以及列匹配确定电路，配置为响应于具有列地址的负载控制信号将对应于故障列的列地址信息进行比较，并产生 列地址替换控制信号，其中响应于列地址替换控制信号，连接到故障段的故障列的存储器单元被连接到备用存储器单元的列的存储器单元替换。

公开(公告)号：US20160148656A1

公开(公告)日：2016-05-26

申请号：US14803119

申请日：2015-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheol KIM ,  Young-soo SOHN ,  Sang-Ho SHIN

IPC: G11C7/10 ,  H01L23/525 ,  G11C8/06 ,  G11C5/06 ,  G11C7/06 ,  H01L25/065 ,  G11C5/02

CPC classification number: G11C8/06 ,  G11C29/76 ,  G11C29/785 ,  H01L25/0657 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory chip includes a chip input-output pad unit, a plurality of semiconductor dies. The chip input-output pad unit includes a plurality of input-output pins connected to an external device and the plurality of semiconductor dies are connected commonly to the chip input-output pad unit and having a full memory capacity respectively. Each semiconductor die includes a die input-output pad unit, a memory region and a conversion block. The die input-output pad unit includes a plurality of input-output terminals respectively connected to the input-output pins of the chip input-output pad unit. The memory region includes an activated region corresponding to a portion of the full memory capacity and a deactivated region corresponding to a remainder portion of the full memory capacity. The conversion block connects the activated region except the deactivated region to the die input-output pad unit.

Abstract translation: 存储器芯片包括芯片输入 - 输出焊盘单元，多个半导体管芯。 芯片输入输出焊盘单元包括连接到外部设备的多个输入输出引脚，并且多个半导体管芯分别连接到芯片输入 - 输出焊盘单元并具有完全存储器容量。 每个半导体管芯包括管芯输入 - 输出焊盘单元，存储区域和转换块。 管芯输入 - 输出焊盘单元包括分别连接到芯片输入 - 输出焊盘单元的输入 - 输出引脚的多个输入 - 输出端子。 存储器区域包括对应于全部存储器容量的一部分的激活区域和对应于完整存储器容量的剩余部分的去激活区域。 转换块将去激活区域之外的激活区域连接到管芯输入 - 输出焊盘单元。