公开(公告)号：US11606126B2

公开(公告)日：2023-03-14

申请号：US17437709

申请日：2019-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunggil Jeon ,  Jaeyoung Huh ,  Younghwa Kim ,  Hyunchul Hong

IPC: H04B7/06 ,  H04B17/12 ,  H04B17/318 ,  H01Q3/26 ,  H04B1/401

Abstract: Disclosed is an electronic device including a housing, an antenna device including at least one antenna element disposed on one surface or inside of a printed circuit board disposed inside the housing and a radio frequency integrated chip (RFIC) for processing a signal in a frequency band, which is transmitted and/or received through the at least one antenna element, a communication circuit, a memory, and a processor configured to detect an external object, which contacts at least part of the housing, based on a change in a beam pattern of a beam formed by the antenna device, determine whether at least some information of the external object is information included in registration object data stored in the memory, and change the beam pattern by using first compensation data, which is stored in the registration object data and which is changed depending on a registration structure corresponding to the external object when the at least some information of the external object is included in the registration object data.

公开(公告)号：US12299296B2

公开(公告)日：2025-05-13

申请号：US18045590

申请日：2022-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghyun Cho ,  Youngju Kim ,  Younghwa Kim ,  Yujung Song ,  Reum Oh

IPC: G11C11/401 ,  G06F3/06 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4097

Abstract: A semiconductor memory device includes a memory cell array, a row decoder and a timing/voltage control circuit. The memory cell array is divided into a plurality of row blocks by one or more row block identity bits, and each of the of row blocks includes sub-array blocks arranged in a first direction. A row address includes the one or more row block identity bits. The row decoder activates a first word-line coupled to a first memory cell, activates a second word-line coupled to a second memory cell in response to the row address, and outputs a row block information signal. The timing/voltage control circuit adjusts at least one of an operation interval and an operation voltage of a memory operation on the first memory cell and the second memory cell according to a distance in a second direction crossing the first direction from a reference position, based on the row block information signal.

公开(公告)号：US20230289072A1

公开(公告)日：2023-09-14

申请号：US18045590

申请日：2022-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghyun Cho ,  Youngju Kim ,  Younghwa Kim ,  Yujung Song ,  Reum Oh

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0673 ,  G06F3/0629 ,  G06F3/064

Abstract: A semiconductor memory device includes a memory cell array, a row decoder and a timing/voltage control circuit. The memory cell array is divided into a plurality of row blocks by one or more row block identity bits, and each of the of row blocks includes sub-array blocks arranged in a first direction. A row address includes the one or more row block identity bits. The row decoder activates a first word-line coupled to a first memory cell, activates a second word-line coupled to a second memory cell in response to the row address, and outputs a row block information signal. The timing/voltage control circuit adjusts at least one of an operation interval and an operation voltage of a memory operation on the first memory cell and the second memory cell according to a distance in a second direction crossing the first direction from a reference position, based on the row block information signal.