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    Word line driver circuits for memory devices and methods of operating same
    1.
    发明授权
    Word line driver circuits for memory devices and methods of operating same 有权

    公开(公告)号：US11450376B2

    公开(公告)日：2022-09-20

    申请号：US17038488

    申请日：2020-09-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sunggeun Do ,  Youngsik Kim ,  Gongheum Han ,  Sangyun Kim ,  Seunghyun Cho

    IPC: G11C11/408 ,  G11C5/06 ,  G11C11/406 ,  G11C11/4074

    Abstract: A memory device includes a word line driver circuit, which can advantageously reduce gate stress on a transistor using a lower high voltage that varies with a command, and an operating method of the memory device. The memory device includes a plurality of memory blocks, provides a high voltage or the lower high voltage to a variable high voltage line in response to a block select signal, and changes a level of the lower high voltage to a low voltage level, a medium voltage level, or a high voltage level based on the command. The memory device applies the lower high voltage to gates of P-type metal oxide semiconductor (PMOS) transistors connected to a word line driving signal, which drives word lines of non-selected memory blocks among the plurality of memory blocks.

    Word line driver circuits for memory devices and methods of operating same
    3.
    发明授权
    Word line driver circuits for memory devices and methods of operating same 有权

    公开(公告)号：US12198749B2

    公开(公告)日：2025-01-14

    申请号：US17819289

    申请日：2022-08-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sunggeun Do ,  Youngsik Kim ,  Gongheum Han ,  Sangyun Kim ,  Seunghyun Cho

    IPC: G11C11/408 ,  G11C5/06 ,  G11C11/406 ,  G11C11/4074

    Abstract: A memory device includes a word line driver circuit, which can advantageously reduce gate stress on a transistor using a lower high voltage that varies with a command, and an operating method of the memory device. The memory device includes a plurality of memory blocks, provides a high voltage or the lower high voltage to a variable high voltage line in response to a block select signal, and changes a level of the lower high voltage to a low voltage level, a medium voltage level, or a high voltage level based on the command. The memory device applies the lower high voltage to gates of P-type metal oxide semiconductor (PMOS) transistors connected to a word line driving signal, which drives word lines of non-selected memory blocks among the plurality of memory blocks.

    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
    4.
    发明公开
    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240098990A1

    公开(公告)日：2024-03-21

    申请号：US18127404

    申请日：2023-03-28

    Applicant: Samsung Electronics Co., Ltd

    Inventor： Sung-Min Hwang ,  Jaehoon Lee ,  Seunghyun Cho ,  Jae-Joo Shim ,  Dong-Sik Lee

    IPC: H01L29/76 ,  H01L23/528

    CPC classification number: H10B41/27 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/35

    Abstract: A semiconductor device includes a gate stack structure including insulating patterns and conductive patterns which are alternately stacked, a first separation structure penetrating the gate stack structure, a second separation structure penetrating the gate stack structure and being adjacent to the first separation structure, first and second memory channel structures penetrating the gate stack structure and disposed between the first separation structure and the second separation structure, a first bit line overlapping with the first and second memory channel structures and electrically connected to the first memory channel structure, and a second bit line overlapping with the first and second memory channel structures and the first bit line and electrically connected to the second memory channel structure.

    WORD LINE DRIVER CIRCUITS FOR MEMORY DEVICES AND METHODS OF OPERATING SAME
    7.
    发明申请
    WORD LINE DRIVER CIRCUITS FOR MEMORY DEVICES AND METHODS OF OPERATING SAME 有权

    公开(公告)号：US20220383932A1

    公开(公告)日：2022-12-01

    申请号：US17819289

    申请日：2022-08-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sunggeun Do ,  Youngsik Kim ,  Gongheum Han ,  Sangyun Kim ,  Seunghyun Cho

    IPC: G11C11/408 ,  G11C5/06 ,  G11C11/406 ,  G11C11/4074

    Abstract: A memory device includes a word line driver circuit, which can advantageously reduce gate stress on a transistor using a lower high voltage that varies with a command, and an operating method of the memory device. The memory device includes a plurality of memory blocks, provides a high voltage or the lower high voltage to a variable high voltage line in response to a block select signal, and changes a level of the lower high voltage to a low voltage level, a medium voltage level, or a high voltage level based on the command. The memory device applies the lower high voltage to gates of P-type metal oxide semiconductor (PMOS) transistors connected to a word line driving signal, which drives word lines of non-selected memory blocks among the plurality of memory blocks.

    MEMORY DEVICE INCLUDING FLEXIBLE COLUMN REPAIR CIRCUIT
    9.
    发明公开
    MEMORY DEVICE INCLUDING FLEXIBLE COLUMN REPAIR CIRCUIT 审中-公开

    公开(公告)号：US20240006013A1

    公开(公告)日：2024-01-04

    申请号：US18296640

    申请日：2023-04-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyungjin Kim ,  Seunghyun Cho

    IPC: G11C29/44 ,  G06F11/10

    CPC classification number: G11C29/4401 ,  G06F11/1044

    Abstract: A memory device includes a memory cell array having a plurality of memory cells therein that span a plurality of rows, which are grouped into segments, and a plurality of columns, which are grouped into ticks. The ticks include normal ticks, and a spare tick that spans at least one redundancy column of memory cells in the memory cell array. A repair circuit is provided, which is configured to: (i) repair a first source address of a first failed column, which spans a plurality of the segments, with a first destination address of a pass column in one of the normal ticks, and then (ii) further repair the first destination address of the pass column with a first redundancy column within the spare tick that corresponds to the first destination address.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    10.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME 审中-公开

    公开(公告)号：US20230289072A1

    公开(公告)日：2023-09-14

    申请号：US18045590

    申请日：2022-10-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seunghyun Cho ,  Youngju Kim ,  Younghwa Kim ,  Yujung Song ,  Reum Oh

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0673 ,  G06F3/0629 ,  G06F3/064

    Abstract: A semiconductor memory device includes a memory cell array, a row decoder and a timing/voltage control circuit. The memory cell array is divided into a plurality of row blocks by one or more row block identity bits, and each of the of row blocks includes sub-array blocks arranged in a first direction. A row address includes the one or more row block identity bits. The row decoder activates a first word-line coupled to a first memory cell, activates a second word-line coupled to a second memory cell in response to the row address, and outputs a row block information signal. The timing/voltage control circuit adjusts at least one of an operation interval and an operation voltage of a memory operation on the first memory cell and the second memory cell according to a distance in a second direction crossing the first direction from a reference position, based on the row block information signal.

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