公开(公告)号：US20240146335A1

公开(公告)日：2024-05-02

申请号：US18336285

申请日：2023-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  Gilyoung Kang ,  Yujung Song ,  Hyeran Kim ,  Chisung Oh

IPC: H03M13/29 ,  G06F3/06 ,  G06F11/10

CPC classification number: H03M13/2909 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array and an on-die error correction code (ECC) engine. The on-die ECC engine, during a write operation, generates a second main data by encoding a first main data with a random binary code, performs an ECC encoding on the second main data to generate a parity data and stores the second main data and the parity data in a target page in the memory cell array. The on-die ECC engine, during a read operation, reads the second main data and the parity data from the target page, performs an ECC decoding on the second main data based on the parity data to generate a syndrome in parallel with generating the first main data by encoding the second main data with the random binary code and corrects at least one error bit in the first main data based on the syndrome.

公开(公告)号：US20230289072A1

公开(公告)日：2023-09-14

申请号：US18045590

申请日：2022-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghyun Cho ,  Youngju Kim ,  Younghwa Kim ,  Yujung Song ,  Reum Oh

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0673 ,  G06F3/0629 ,  G06F3/064

Abstract: A semiconductor memory device includes a memory cell array, a row decoder and a timing/voltage control circuit. The memory cell array is divided into a plurality of row blocks by one or more row block identity bits, and each of the of row blocks includes sub-array blocks arranged in a first direction. A row address includes the one or more row block identity bits. The row decoder activates a first word-line coupled to a first memory cell, activates a second word-line coupled to a second memory cell in response to the row address, and outputs a row block information signal. The timing/voltage control circuit adjusts at least one of an operation interval and an operation voltage of a memory operation on the first memory cell and the second memory cell according to a distance in a second direction crossing the first direction from a reference position, based on the row block information signal.

公开(公告)号：US12170533B2

公开(公告)日：2024-12-17

申请号：US18336285

申请日：2023-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  Gilyoung Kang ,  Yujung Song ,  Hyeran Kim ,  Chisung Oh

IPC: H03M13/29 ,  G06F3/06 ,  G06F11/10 ,  G11C11/4096 ,  G11C29/42 ,  G11C29/52 ,  H03M13/15

Abstract: A semiconductor memory device includes a memory cell array and an on-die error correction code (ECC) engine. The on-die ECC engine, during a write operation, generates a second main data by encoding a first main data with a random binary code, performs an ECC encoding on the second main data to generate a parity data and stores the second main data and the parity data in a target page in the memory cell array. The on-die ECC engine, during a read operation, reads the second main data and the parity data from the target page, performs an ECC decoding on the second main data based on the parity data to generate a syndrome in parallel with generating the first main data by encoding the second main data with the random binary code and corrects at least one error bit in the first main data based on the syndrome.

公开(公告)号：US20240029808A1

公开(公告)日：2024-01-25

申请号：US18174186

申请日：2023-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yujung Song ,  Sungrae Kim ,  Gilyoung Kang ,  Hyeran Kim ,  Chisung Oh

IPC: G11C29/42 ,  G11C29/46 ,  G11C29/12

CPC classification number: G11C29/42 ,  G11C29/46 ,  G11C29/1201

Abstract: A semiconductor memory device includes a memory cell array, an on-die error correction code (ECC) engine and a control logic circuit. The on-die ECC engine includes a first latch and a second latch. The control logic circuit sets the semiconductor memory device to a test mode in response to a first mode register set command. The on-die ECC engine, in the test mode, cuts off a connection with the memory cell array, receives a test data, stores the test data in the first latch, performs an ECC decoding on the test data stored in the first latch and a test parity data, stored in the second latch in response to a read command and provides an external device with a severity signal indicating whether the test data and the test parity data includes at least one error bit and the at least one error bit is correctable.