公开(公告)号：US20240281402A1

公开(公告)日：2024-08-22

申请号：US18460954

申请日：2023-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Jung ,  Younghyun Lee ,  Yongsuk Kwon ,  Kyungsoo Kim ,  Jinin So

IPC: G06F13/42

CPC classification number: G06F13/4282 ,  G06F2213/0002

Abstract: A computing system includes an interconnect device, a plurality of memory devices electrically coupled to communicate with the interconnect device, a plurality of host devices electrically coupled to communicate with the interconnect device and configured to generate requests for access to the plurality of memory devices via the interconnect device, and a plurality of congestion monitors. These congestion monitors are configured to generate congestion information by monitoring a congestion degree of signal transfers with respect to at least one of the plurality of memory devices and the interconnect device in real time. The computing system is also configured to control at least one of: a memory region allocation of the plurality of host devices to the plurality of memory devices, and a signal transfer path inside the interconnect device, based on the congestion information.

公开(公告)号：US20240394331A1

公开(公告)日：2024-11-28

申请号：US18608453

申请日：2024-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangsu PARK ,  Kyungsoo Kim ,  Nayeon Kim ,  Jinin So ,  Kyoungwan Woo ,  Younghyun Lee ,  Jong-Geon Lee ,  Jin Jung ,  Jeonghyeon Cho

IPC: G06F17/16 ,  G06F7/501 ,  G06F13/42

Abstract: A compute express link (CXL) memory device includes a memory device storing data, and a controller configured to read the data from the memory device based on a first command received through a first protocol, select a calculation engine based on a second command received through a second protocol different from the first protocol, and control the calculation engine to perform a calculation on the read data.