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公开(公告)号:US12232260B2
公开(公告)日:2025-02-18
申请号:US17939546
申请日:2022-09-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Seungjin Lee , Jonghoon Kim , Kyoungsun Kim , Sungjoo Park , Jinseong Yun , Young-Ho Lee , Jeonghyeon Cho , Heejin Cho
Abstract: An electronic device includes: a multilayered base substrate including a plurality of substrate bases stacked on each other; a first conductive via and a second conductive via penetrating the substrate bases and spaced from each other; a conductive line electrically connecting the first conductive via and the second conductive via to each other and disposed on at least one of the substrate bases of the plurality of substrate bases; and an open stub including a first end and a second end, wherein the first end is connected to a connector of the conductive line, and the second end is opened.
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公开(公告)号:US12079146B2
公开(公告)日:2024-09-03
申请号:US17383056
申请日:2021-07-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jeonghyeon Cho , Yongsuk Kwon , Kyungsoo Kim , Jonghoon Kim , Jonghyun Seok , Jonggeon Lee
IPC: H05K1/02 , G06F1/20 , G06F1/30 , G06F13/12 , G06F13/16 , G06F13/364 , G06F13/40 , G11C5/04 , G11C5/06 , G11C7/10 , H05K1/14 , H05K1/16 , H05K1/18 , H05K3/36 , H05K7/02 , H05K7/20
CPC classification number: G06F13/1673 , G06F13/4068 , G06F13/409 , G11C5/06 , G11C7/1063
Abstract: A memory module includes a memory substrate including a main connector and an auxiliary connector, configured to be connected to an external device; and a plurality of memory chips mounted on at least one of a first surface or a second surface of the memory substrate, wherein the main connector is disposed on one side of the memory substrate, and the auxiliary connector is disposed on the second surface of the memory substrate.
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公开(公告)号:US20220027090A1
公开(公告)日:2022-01-27
申请号:US17154030
申请日:2021-01-21
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yongsuk Kwon , Jinin So , Jonggeon Lee , Kyungsoo Kim , Jin Jung , Jeonghyeon Cho
Abstract: Memory modules and memory systems having the same are provided. A memory module may include command/address terminals, data terminals, at least one monitoring terminal, a buffer, and a plurality of semiconductor memory devices. The buffer may be configured to receive and buffer data applied through the data terminals and a command/address applied through the command/address terminals to generate buffered write data and a buffered command/address. The buffer may be configured to buffer the buffered write data and the buffered command/address to generate module data and a module command/address, and store and then transmit at least one portion of the buffered write data as monitoring data through the at least one monitoring terminal. The plurality of semiconductor memory devices may be configured to receive and store the module data in response to the module command/address.
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公开(公告)号:US20240394331A1
公开(公告)日:2024-11-28
申请号:US18608453
申请日:2024-03-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sangsu PARK , Kyungsoo Kim , Nayeon Kim , Jinin So , Kyoungwan Woo , Younghyun Lee , Jong-Geon Lee , Jin Jung , Jeonghyeon Cho
Abstract: A compute express link (CXL) memory device includes a memory device storing data, and a controller configured to read the data from the memory device based on a first command received through a first protocol, select a calculation engine based on a second command received through a second protocol different from the first protocol, and control the calculation engine to perform a calculation on the read data.
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5.
公开(公告)号:US11620135B2
公开(公告)日:2023-04-04
申请号:US17115924
申请日:2020-12-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jonggeon Lee , Kyungsoo Kim , Jinin So , Yongsuk Kwon , Jin Jung , Jeonghyeon Cho
IPC: G06F9/00 , G06F9/4401 , G06N20/00
Abstract: A booting method of a computing system, which includes a memory module including a processing device connected to a plurality of memory devices, including: powering up the computing system; after powering up the computing system, performing first memory training on the plurality of memory devices by the processing device in the memory module, and generating a module ready signal indicating completion of the first memory training; after powering up the computing system, performing a first booting sequence by a host device, the host device executing basic input/output system (BIOS) code of a BIOS memory included in the computing system; waiting for the module ready signal to be received from the memory module in the host device after performing the first booting sequence; and receiving the module ready signal in the host device, and performing a second booting sequence based on the module ready signal.
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公开(公告)号:US20230028071A1
公开(公告)日:2023-01-26
申请号:US17715158
申请日:2022-04-07
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jonggeon Lee , Jinin So , Yongsuk Kwon , Kyungsoo Kim , Ilkwon Yun , Jeonghyeon Cho
Abstract: A memory module includes a device memory configured to store data and including a first memory area and a second memory area, and a controller including an accelerator circuit. The controller is configured to control the device memory, transmit a command to exclude the first memory area from the system memory map to a host processor in response to a mode change request, and modify a memory configuration register to exclude the first memory area from the memory configuration register. The accelerator circuit is configured to use the first memory area to perform an acceleration operation.
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公开(公告)号:US11531496B2
公开(公告)日:2022-12-20
申请号:US17154030
申请日:2021-01-21
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yongsuk Kwon , Jinin So , Jonggeon Lee , Kyungsoo Kim , Jin Jung , Jeonghyeon Cho
Abstract: Memory modules and memory systems having the same are provided. A memory module may include command/address terminals, data terminals, at least one monitoring terminal, a buffer, and a plurality of semiconductor memory devices. The buffer may be configured to receive and buffer data applied through the data terminals and a command/address applied through the command/address terminals to generate buffered write data and a buffered command/address. The buffer may be configured to buffer the buffered write data and the buffered command/address to generate module data and a module command/address, and store and then transmit at least one portion of the buffered write data as monitoring data through the at least one monitoring terminal. The plurality of semiconductor memory devices may be configured to receive and store the module data in response to the module command/address.
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公开(公告)号:US11133040B2
公开(公告)日:2021-09-28
申请号:US16852986
申请日:2020-04-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jeonghyeon Cho , Seonghoon Joo , Ilhan Choi
Abstract: A semiconductor memory device includes: a temperature sensor configured to sense an internal temperature of the semiconductor memory device and generate a temperature signal; and a temperature code storage unit configured to receive the temperature signal in response to a temperature code write control signal that is generated when an operation corresponding to a specific command is performed, generate an operating temperature code corresponding to the temperature signal, compare the operating temperature code with a previously stored temperature code, store a larger temperature code of the operating temperature code and the previously stored temperature code as a maximum temperature code, and output the maximum temperature code to an external source in response to a temperature code read control signal.
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公开(公告)号:US11531618B2
公开(公告)日:2022-12-20
申请号:US17157323
申请日:2021-01-25
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kyungsoo Kim , Jinin So , Jong-Geon Lee , Yongsuk Kwon , Jin Jung , Jeonghyeon Cho
IPC: G06F12/0804 , G06F11/20 , G11C11/4093 , G11C11/4096 , H04N21/426
Abstract: A memory module includes a first memory device, a second memory device, and a processing buffer circuit that is connected to the first memory device and the second memory device (independently of each other) and a host. A processing buffer circuit is provided, which includes a processing circuit and a buffer. The processing circuit processes at least one of data received from the host, data stored in the first memory device, or data stored in the second memory device based on a processing command received from the host. The buffer is configured to store data processed by the processing circuit. The processing buffer circuit is configured to communicate with the host in compliance with a DDR SDRAM standard.
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公开(公告)号:US20210390049A1
公开(公告)日:2021-12-16
申请号:US17157323
申请日:2021-01-25
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kyungsoo Kim , Jinin So , Jong-Geon Lee , Yongsuk Kwon , Jin Jung , Jeonghyeon Cho
IPC: G06F12/0804 , G06F11/20 , G11C11/4096 , G11C11/4093
Abstract: A memory module includes a first memory device, a second memory device, and a processing buffer circuit that is connected to the first memory device and the second memory device (independently of each other) and a host. A processing buffer circuit is provided, which includes a processing circuit and a buffer. The processing circuit processes at least one of data received from the host, data stored in the first memory device, or data stored in the second memory device based on a processing command received from the host. The buffer is configured to store data processed by the processing circuit. The processing buffer circuit is configured to communicate with the host in compliance with a DDR SDRAM standard.
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