ELECTRONIC DEVICE MOUNTED TO VEHICLE AND OPERATION METHOD THEREOF

    公开(公告)号:US20240353996A1

    公开(公告)日:2024-10-24

    申请号:US18758413

    申请日:2024-06-28

    Abstract: An electronic device mounted in a vehicle, and an method performed thereby are provided. The electronic device may include a touch screen, memory storing at least one instruction, and at least one processor communicatively coupled to the touch screen and the memory. The at least one instruction, when executed by the at least one processor individually or collectively, may cause the electronic device to recognize an input event, based on receiving a multi-touch input or a hover input, of a user with respect to the touch screen, may identify a function corresponding to the input event, based on shape information of a plurality of points and position information of the plurality of points at which the input event is recognized, may change a function value with respect to the identified function, based on a gesture input being recognized via the touch screen, and may display a user interface (UI) indicating the changed function value.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

    公开(公告)号:US20230301068A1

    公开(公告)日:2023-09-21

    申请号:US18118766

    申请日:2023-03-08

    CPC classification number: H10B12/315 H01L23/5283 H10B12/05

    Abstract: A semiconductor memory device includes a substrate, contact electrodes extending in a first direction, each of the contact electrodes including a connection portion having a first thickness and a landing portion having a second thickness, an uppermost contact electrode above the contact electrodes, the contact electrodes being longer in the first direction than the uppermost contact electrode and defining a step structure, transistor bodies extending in a second direction and having a first source/drain, a monocrystalline channel layer, and a second source/drain sequentially arranged in the second direction, the monocrystalline channel layer being connected to a corresponding contact electrode, a lower electrode layer connected to the second source/drain of each of the transistor bodies, a capacitor dielectric layer covering the lower electrode layer and having a uniform thickness, and an upper electrode layer separated from the lower electrode layer by the capacitor dielectric layer.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME

    公开(公告)号:US20230209826A1

    公开(公告)日:2023-06-29

    申请号:US18080325

    申请日:2022-12-13

    CPC classification number: H01L27/11582 H01L23/535 H01L27/11573

    Abstract: A three-dimensional semiconductor memory device includes a substrate including a first region and a second region, the second region extending from the first region; a stack including interlayer insulating layers and gate electrodes, which are alternately and repeatedly stacked on the substrate, the stack having a staircase structure on the second region; an insulating layer covering the staircase structure of the stack; first vertical channel structures on the first region, penetrating the stack, and in contact with the substrate; first contact plugs on the second region and penetrating the insulating layer and the stack; and first insulating pads in the insulating layer and enclosing upper portions of the first contact plugs, respectively, wherein the first insulating pads overlap with the first vertical channel structures in a horizontal direction.

    STORAGE DEVICE AND OPERATING METHOD THEREOF
    5.
    发明公开

    公开(公告)号:US20230142479A1

    公开(公告)日:2023-05-11

    申请号:US17978415

    申请日:2022-11-01

    CPC classification number: G06F3/0619 G06F3/0653 G06F3/0659 G06F3/0679

    Abstract: Provided are a storage device and an operating method thereof. The storage device includes a non-volatile memory including a plurality of memory regions and a storage controller configured to control the non-volatile memory through a performance path and at least one direct path, the storage controller including a buffer memory configured to store recovery data, wherein the storage controller writes the recovery data to the non-volatile memory through the at least one direct path in response to power being cut off and a fault being detected in the performance path, the performance path is a path for performing a write operation, a read operation, and an erase operation, and the at least one direct path is a path for performing only a write operation.

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