公开(公告)号：US20210050049A1

公开(公告)日：2021-02-18

申请号：US16809016

申请日：2020-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seheon BAEK ,  Youngsun MIN

IPC: G11C11/4091 ,  G11C11/4094 ,  G11C11/4093 ,  G11C11/4074 ,  G11C7/22 ,  G11C7/10 ,  G11C5/02

Abstract: A memory device includes a first page buffer supplying a first bias voltage to a selected bitline in a bitline precharge phase; and a second page buffer supplying a second bias voltage to an unselected bitline, adjacent to the selected bitline, in the bitline precharge phase, wherein the first page buffer includes a first bitline precharge circuit supplying the first bias voltage to the selected bitline, the second page buffer includes a second bitline precharge circuit supplying the second bias voltage to the unselected bitline, wherein the second page buffer floats the unselected bitline in a sensing phase for detecting data of a selected memory cell connected to the selected to bitline.

公开(公告)号：US20210066281A1

公开(公告)日：2021-03-04

申请号：US16944711

申请日：2020-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehong KWON ,  Youngsun MIN ,  Daeseok BYEON ,  Kyunghwa YUN

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/065 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: A memory device includes a memory cell array, a row decoder connected to the memory cell array by a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines, and a common source line driver connected to the memory cell array by a common source line. The memory cell array is located in an upper chip, at least a portion of the row decoder is located in a lower chip, at least a portion of the common source line driver is located in the upper chip, and a plurality of upper bonding pads of the upper chip are connected to a plurality of lower bonding pads of the lower chip to connect the upper chip to the lower chip.

公开(公告)号：US20210065801A1

公开(公告)日：2021-03-04

申请号：US16862167

申请日：2020-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehong KWON ,  Youngsun MIN ,  Daeseok BYEON ,  Kyunghwa YUN

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  G11C16/10 ,  G11C16/30 ,  G11C16/24

Abstract: A memory device includes a memory cell array, a row decoder connected to the memory cell array by a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines, and a common source line driver connected to the memory cell array by a common source line. The memory cell array is located in an upper chip, at least a portion of the row decoder is located in a lower chip, at least a portion of the common source line driver is located in the upper chip, and a plurality of upper bonding pads of the upper chip are connected to a plurality of lower bonding pads of the lower chip to connect the upper chip to the lower chip.