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    VERTICAL CAPACITOR STRUCTURE AND NON-VOLATILE MEMORY DEVICE INCLUDING THE SAME
    1.
    发明申请
    VERTICAL CAPACITOR STRUCTURE AND NON-VOLATILE MEMORY DEVICE INCLUDING THE SAME 审中-公开

    公开(公告)号：US20200321349A1

    公开(公告)日：2020-10-08

    申请号：US16662073

    申请日：2019-10-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taehong KWON ,  Chanho KIM ,  Daeseok BYEON ,  Pansuk KWAK ,  Chiweon YOON

    IPC: H01L27/11573 ,  H01L27/11582 ,  H01L29/94 ,  H01L29/78

    Abstract: A non-volatile memory device includes a substrate, a memory cell string including a vertical channel structure and memory cells, a voltage generator including a first transistor and configured to provide various voltages to the memory cells, and a vertical capacitor structure. The vertical capacitor structure includes first and second active patterns apart from each other in a first horizontal direction, a first gate pattern located above a channel region between the first and second active patterns, a first gate insulating film between the first gate pattern and the substrate in a vertical direction, and capacitor electrodes each extending in the vertical direction. The first transistor includes a second gate pattern and a second gate insulating film between the second gate pattern and the substrate in the vertical direction. The first gate insulating film has a thickness greater than a thickness of the second gate insulating film in the vertical direction.

    MEMORY DEVICE AND REPAIR METHOD OF THE MEMORY DEVICE
    3.
    发明公开
    MEMORY DEVICE AND REPAIR METHOD OF THE MEMORY DEVICE 审中-公开

    公开(公告)号：US20240257898A1

    公开(公告)日：2024-08-01

    申请号：US18425747

    申请日：2024-01-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taehong KWON ,  Daeseok Byeon

    IPC: G11C29/00

    CPC classification number: G11C29/702 ,  G11C29/781 ,  G11C29/789

    Abstract: A memory device is provided. The memory device includes: a first cell region provided in a first layer and including a first bit line and a first redundant bit line; a second cell region provided in a second layer and including a second bit line and a second redundant bit line; a peripheral region provided in a third layer and including first page buffers configured to be respectively connected to the first bit line and the second bit line, and a second page buffer configured to be commonly connected to the first redundant bit line and the second redundant bit line; and a control circuit configured to: based on the first bit line being defective, replace the first bit line with the first redundant bit line; and based on the second bit line being defective, replace the second bit line with the second redundant bit line.

    MEMORY DEVICE
    5.
    发明申请
    MEMORY DEVICE 有权

    公开(公告)号：US20210066281A1

    公开(公告)日：2021-03-04

    申请号：US16944711

    申请日：2020-07-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taehong KWON ,  Youngsun MIN ,  Daeseok BYEON ,  Kyunghwa YUN

    IPC: H01L25/18 ,  H01L23/00 ,  H01L25/065 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

    Abstract: A memory device includes a memory cell array, a row decoder connected to the memory cell array by a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines, and a common source line driver connected to the memory cell array by a common source line. The memory cell array is located in an upper chip, at least a portion of the row decoder is located in a lower chip, at least a portion of the common source line driver is located in the upper chip, and a plurality of upper bonding pads of the upper chip are connected to a plurality of lower bonding pads of the lower chip to connect the upper chip to the lower chip.

    MEMORY DEVICE
    6.
    发明申请
    MEMORY DEVICE 有权

    公开(公告)号：US20210065801A1

    公开(公告)日：2021-03-04

    申请号：US16862167

    申请日：2020-04-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taehong KWON ,  Youngsun MIN ,  Daeseok BYEON ,  Kyunghwa YUN

    IPC: G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  G11C16/10 ,  G11C16/30 ,  G11C16/24

    Abstract: A memory device includes a memory cell array, a row decoder connected to the memory cell array by a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines, and a common source line driver connected to the memory cell array by a common source line. The memory cell array is located in an upper chip, at least a portion of the row decoder is located in a lower chip, at least a portion of the common source line driver is located in the upper chip, and a plurality of upper bonding pads of the upper chip are connected to a plurality of lower bonding pads of the lower chip to connect the upper chip to the lower chip.

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