公开(公告)号：US20220336664A1

公开(公告)日：2022-10-20

申请号：US17558967

申请日：2021-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deok Han BAE ,  Ju Hun PARK ,  Myung Yoon UM ,  Yu Ri LEE ,  In Yeal LEE

IPC: H01L29/78 ,  H01L29/08

Abstract: A semiconductor device is capable of improving the performance and reliability of a device. The semiconductor device includes a first fin-shaped pattern which extends lengthwise in a first direction, a second fin-shaped pattern which is spaced apart from the first fin-shaped pattern in a second direction and extends lengthwise in the first direction, a first gate electrode extending lengthwise in the second direction on the first fin-shaped pattern, a second gate electrode extending lengthwise in the second direction on the second fin-shaped pattern, a first gate separation structure which separates the first gate electrode and the second gate electrode and is at the same vertical level as the first gate electrode and the second gate electrode, and a first source/drain contact extending lengthwise in the second direction on the first fin-shaped pattern and the second fin-shaped pattern. The first source/drain contact includes a first lower source/drain contact region which intersects the first fin-shaped pattern and the second fin-shaped pattern, and a first upper source/drain contact region which protrudes from the first lower source/drain contact region, and the first upper source/drain contact region does not overlap the first gate separation structure in the first direction.

公开(公告)号：US20230352591A1

公开(公告)日：2023-11-02

申请号：US17989944

申请日：2022-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Deok Han BAE ,  Myung Yoon UM ,  Yu Ri LEE ,  Sun Me LIM ,  Jun Su JEON

IPC: H01L29/78 ,  H01L29/417 ,  H01L23/528 ,  H01L23/522 ,  H01L27/088

CPC classification number: H01L29/7851 ,  H01L29/41791 ,  H01L23/5283 ,  H01L23/5226 ,  H01L27/0886

Abstract: A semiconductor device includes an isolation structure having first and second sidewalls opposite each other, a first fin-shaped pattern in contact with the first sidewall and extending in the second direction, a second fin-shaped pattern in contact with the second sidewall and extending in the second direction, a first gate electrode on the first fin-shaped pattern, a first source/drain contact on the first and second fin-shaped patterns and extending between the first gate electrode and the element isolation structure, and a wiring structure on and connected to the first source/drain contact, wherein the first source/drain contact includes a lower contact intersecting the first and second fin-shaped patterns, an upper contact protruding from the lower contact, and a dummy contact, the wiring structure being in contact with the upper contact and not with the dummy contact.