公开(公告)号：US20220037461A1

公开(公告)日：2022-02-03

申请号：US17189700

申请日：2021-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gihee CHO ,  Sangyeol KANG ,  Jungoo KANG ,  Taekyun KIM ,  Jiwoon PARK ,  Sanghyuck AHN ,  Jin-Su LEE ,  Hyun-Suk LEE ,  Hongsik CHAE

IPC: H01L49/02 ,  H01L27/108

Abstract: A semiconductor device and a method of manufacturing the same, the device including a plurality of lower electrodes on a semiconductor substrate; a support pattern connecting the lower electrodes at sides of the lower electrodes; and a dielectric layer covering the lower electrodes and the support pattern, wherein each of the plurality of lower electrodes includes a pillar portion extending in a vertical direction perpendicular to a top surface of the semiconductor substrate; and a protrusion protruding from a sidewall of the pillar portion so as to be in contact with the support pattern, the pillar portion includes a conductive material, the protrusion includes a same conductive material as the pillar portion and is further doped with impurities.

公开(公告)号：US20220336578A1

公开(公告)日：2022-10-20

申请号：US17857383

申请日：2022-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gihee CHO ,  Sangyeol KANG ,  Jungoo KANG ,  Taekyun KIM ,  Jiwoon PARK ,  Sanghyuck AHN ,  Jin-Su LEE ,  Hyun-Suk LEE ,  Hongsik CHAE

IPC: H01L49/02 ,  H01L27/108

Abstract: A semiconductor device and a method of manufacturing the same, the device including a plurality of lower electrodes on a semiconductor substrate; a support pattern connecting the lower electrodes at sides of the lower electrodes; and a dielectric layer covering the lower electrodes and the support pattern, wherein each of the plurality of lower electrodes includes a pillar portion extending in a vertical direction perpendicular to a top surface of the semiconductor substrate; and a protrusion protruding from a sidewall of the pillar portion so as to be in contact with the support pattern, the pillar portion includes a conductive material, the protrusion includes a same conductive material as the pillar portion and is further doped with impurities.

公开(公告)号：US20160104763A1

公开(公告)日：2016-04-14

申请号：US14863820

申请日：2015-09-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunjung CHOI ,  Se Hoon OH ,  Jin-Su LEE ,  Younsoo KIM ,  HanJin LIM

IPC: H01L49/02

CPC classification number: H01L28/75 ,  H01L28/90

Abstract: A semiconductor device includes a lower electrode on a lower structure, a dielectric layer conformally covering a surface of the lower electrode, an upper electrode conformally covering a surface of the dielectric layer, and a barrier layer on the upper electrode. The barrier layer and the upper electrode define a space on a sidewall of the lower electrode.

Abstract translation: 半导体器件包括下部结构的下部电极，保形地覆盖下部电极的表面的电介质层，保持覆盖电介质层的表面的上部电极和上部电极上的阻挡层。 阻挡层和上电极在下电极的侧壁上形成空间。

公开(公告)号：US20160027896A1

公开(公告)日：2016-01-28

申请号：US14669221

申请日：2015-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Su LEE ,  Young-Wook PARK ,  Hee-Sook PARK ,  Dong-Bok LEE ,  Jong-Myeong LEE

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/288 ,  H01L21/02 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L21/31111 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/288 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76855 ,  H01L21/76879 ,  H01L21/76895 ,  H01L27/10855 ,  H01L29/4236 ,  H01L29/78

Abstract: Semiconductor devices, and methods for fabricating a semiconductor device, include forming a contact hole penetrating an interlayer insulating layer and exposing a conductor defining a bottom surface of the contact hole, forming a sacrificial layer filling the contact hole, forming a first trench overlapping a part of the contact hole by removing at least a part of the sacrificial layer, forming a spacer filling the first trench, forming a second trench by removing a remainder of the sacrificial layer, and forming a metal electrode filling the contact hole and the second trench using electroless plating.

Abstract translation: 半导体器件以及半导体器件的制造方法包括：形成贯穿层间绝缘层的接触孔，露出限定接触孔的底面的导体，形成填充接触孔的牺牲层，形成与第一沟槽重叠的部分 通过去除所述牺牲层的至少一部分，形成填充所述第一沟槽的间隔物，通过去除所述牺牲层的剩余部分形成第二沟槽，以及使用以下方式形成填充所述接触孔和所述第二沟槽的金属电极： 无电镀。

公开(公告)号：US20140120683A1

公开(公告)日：2014-05-01

申请号：US14028976

申请日：2013-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyongsoo KIM ,  Jin-Su LEE ,  Hojun KWON ,  Dongkyun PARK ,  Jiseung LEE ,  Young-Seok CHOI

IPC: H01L49/02

CPC classification number: H01L27/10817 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/91

Abstract: Capacitor of a semiconductor device, and a method of fabricating the same, include sequentially forming a mold structure and a polysilicon pattern over a semiconductor substrate, patterning the mold structure using the polysilicon pattern as an etch mask to form lower electrode holes penetrating the mold structure, forming a protection layer covering a surface of the polysilicon pattern, forming lower electrodes in the lower electrode holes provided with the protection layer, removing the polysilicon pattern and the protection layer to expose upper sidewalls of the lower electrodes, removing the mold structure to expose lower sidewalls of the lower electrodes, and sequentially forming a dielectric and an upper electrode covering the lower electrodes.

Abstract translation: 半导体器件的电容器及其制造方法包括在半导体衬底上顺序地形成模具结构和多晶硅图案，使用多晶硅图案将模具结构图案化为蚀刻掩模，以形成贯穿模具结构的下部电极孔 形成覆盖多晶硅图案的表面的保护层，在设置有保护层的下电极孔中形成下电极，去除多晶硅图案和保护层以暴露下电极的上侧壁，去除模具结构暴露 下电极的下侧壁，并且依次形成覆盖下电极的电介质和上电极。

公开(公告)号：US20230337412A1

公开(公告)日：2023-10-19

申请号：US17968464

申请日：2022-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihoon AN ,  Jin-Su LEE ,  Hongsik CHAE ,  Donguk HAN

IPC: H01L27/108

CPC classification number: H01L27/10814 ,  H01L27/10852

Abstract: A semiconductor device includes a substrate, a capacitor contact structure electrically connected to the substrate, and a lower electrode connected to the capacitor contact structure. The lower electrode includes a first electrode layer and a second electrode layer, the second electrode layer is on the first electrode layer, and the first electrode layer includes a group 14 element. The device includes a capacitor insulating layer covering the lower electrode, and an upper electrode covering the capacitor insulating layer. The first electrode layer includes an outer sidewall in contact with the capacitor insulating layer, the first electrode layer includes an inner sidewall in contact with the second electrode layer, and a concentration of the group 14 element in the inner sidewall of the first electrode layer is higher than a concentration of the group 14 element in the outer sidewall of the first electrode layer.