公开(公告)号：US20160104763A1

公开(公告)日：2016-04-14

申请号：US14863820

申请日：2015-09-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunjung CHOI ,  Se Hoon OH ,  Jin-Su LEE ,  Younsoo KIM ,  HanJin LIM

IPC: H01L49/02

CPC classification number: H01L28/75 ,  H01L28/90

Abstract: A semiconductor device includes a lower electrode on a lower structure, a dielectric layer conformally covering a surface of the lower electrode, an upper electrode conformally covering a surface of the dielectric layer, and a barrier layer on the upper electrode. The barrier layer and the upper electrode define a space on a sidewall of the lower electrode.

Abstract translation: 半导体器件包括下部结构的下部电极，保形地覆盖下部电极的表面的电介质层，保持覆盖电介质层的表面的上部电极和上部电极上的阻挡层。 阻挡层和上电极在下电极的侧壁上形成空间。

公开(公告)号：US20170194158A1

公开(公告)日：2017-07-06

申请号：US15398776

申请日：2017-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Kwan YU ,  Woonki SHIN ,  Moonhan PARK ,  DongSuk SHIN ,  HanJin LIM

IPC: H01L21/306 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L21/30604 ,  H01L21/02057 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481

Abstract: An etching method is disclosed. The etching method comprises providing on a substrate a structure comprising a recess region formed therein. The recess region includes an inner part and a mouth part whose width is less than that of the inner part. The etching method further comprises performing a clean-then-etch process to remove at least a portion of etching object formed outside the recess region. The performing a clean-then-etch process comprises performing a cleaning process to fill at least a portion of the recess region with a cleaning solution, and performing a wet etch process to the substrate in a state that the cleaning solution remains in the recess region.

公开(公告)号：US20140264517A1

公开(公告)日：2014-09-18

申请号：US14175076

申请日：2014-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngkuk KIM ,  Ho-Kyun AN ,  Jaehyun YEO ,  Badro IM ,  HanJin LIM ,  Sungho JANG ,  Insang JEON

IPC: H01L27/108 ,  H01L27/105

CPC classification number: H01L27/10894 ,  H01L21/823412 ,  H01L21/823462 ,  H01L27/10814 ,  H01L27/10861

Abstract: Semiconductor devices having a silicon-germanium channel layer and methods of forming the semiconductor devices are provided. The methods may include forming a silicon-germanium channel layer on a substrate in a peripheral circuit region and sequentially forming a first insulating layer and a second insulating layer on the silicon-germanium channel layer. The methods may also include forming a conductive layer on the substrate, which includes a cell array region and the peripheral circuit region, and patterning the conductive layer to form a conductive line in the cell array region and a gate electrode in the peripheral circuit region. The first insulating layer may be formed at a first temperature and the second insulating layer may be formed at a second temperature higher than the first temperature.

Abstract translation: 提供具有硅 - 锗沟道层的半导体器件和形成半导体器件的方法。 所述方法可以包括在外围电路区域中的衬底上形成硅 - 锗沟道层，并且在硅 - 锗沟道层上依次形成第一绝缘层和第二绝缘层。 该方法还可以包括在衬底上形成导电层，该导电层包括电池阵列区域和外围电路区域，以及图案化导电层以在电池阵列区域中形成导线以及在外围电路区域中形成栅极电极。 第一绝缘层可以在第一温度下形成，并且第二绝缘层可以在高于第一温度的第二温度下形成。