公开(公告)号：US20240170372A1

公开(公告)日：2024-05-23

申请号：US18347765

申请日：2023-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungwoo LEE ,  Yunsuk Nam ,  Jinkyu Kim ,  Sora You ,  Sungmoon Lee ,  Seungmin Cha

IPC: H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device may include first active patterns adjacent to each other on a substrate, first source/drain patterns respectively on the first active patterns and adjacent to each other, a first division structure and a second division structure crossing the first active patterns and arranged on the substrate such that adjacent ones of the first source/drain patterns are interposed between the first division structure and the second division structure, a first penetration via between adjacent ones of the first source/drain patterns, a first power line on the first penetration via and electrically connected to the first penetration via, a power delivery network layer on a bottom surface of the substrate, and a first lower penetration via between the power delivery network layer and the first penetration via.

公开(公告)号：US20240413204A1

公开(公告)日：2024-12-12

申请号：US18615708

申请日：2024-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeewoong KIM ,  Hidenobu Fukutome ,  Jinkyu Kim ,  Yunsuk Nam ,  Dongyun Lee

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes: insulating patterns spaced apart from each other in a first direction and in a second direction that intersects the first direction; a substrate insulating layer on first side surfaces of the insulating patterns; a device isolation layer on second side surfaces of the insulating patterns; channel layers on the insulating patterns and spaced apart from each other in a vertical direction that is perpendicular to an upper surface of the device isolation layer; gate structures vertically overlapping the insulating patterns, surrounding each of the channel layers, and extending in the second direction; source/drain regions provided outside the gate structures; and backside contact structures electrically connected to the source/drain regions and provided below the source/drain regions, wherein the insulating patterns include protrusions protruding in the vertical direction from an upper surface of the device isolation layer, and, in a region in which the insulating patterns vertically overlap the gate structures, a vertical distance between a lower surface of a lowermost channel layer among the channel layers and an upper surface of the protrusions is greater than a vertical distance between the channel layers.