公开(公告)号：US20240030326A1

公开(公告)日：2024-01-25

申请号：US18159200

申请日：2023-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sora YOU ,  Kyoungwoo Lee ,  Sungmoon Lee ,  Seungmin Cha ,  Hagju Cho

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/775 ,  H01L27/088 ,  H01L29/42392 ,  H01L29/0673

Abstract: A semiconductor device includes parallel active regions on a substrate and extending in a first horizontal direction; gate structures intersecting the active regions, extending in a second horizontal direction, and including first and second gate structures opposing each other in the second horizontal direction; source/drain regions including first and second source/drain regions, on at least one side of the gate structures and on the active regions; a gate separation pattern between the first and second gate structures; a vertical conductive structure in the gate separation pattern; contact plugs including a first contact plug electrically connected to the first source/drain region and the vertical conductive structure, and a second contact plug electrically connected to the second source/drain region and spaced apart from the vertical conductive structure; and a contact separation pattern separating the first and second contact plugs, having a portion contacting an upper surface of the vertical conductive structure.

公开(公告)号：US20240170372A1

公开(公告)日：2024-05-23

申请号：US18347765

申请日：2023-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungwoo LEE ,  Yunsuk Nam ,  Jinkyu Kim ,  Sora You ,  Sungmoon Lee ,  Seungmin Cha

IPC: H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device may include first active patterns adjacent to each other on a substrate, first source/drain patterns respectively on the first active patterns and adjacent to each other, a first division structure and a second division structure crossing the first active patterns and arranged on the substrate such that adjacent ones of the first source/drain patterns are interposed between the first division structure and the second division structure, a first penetration via between adjacent ones of the first source/drain patterns, a first power line on the first penetration via and electrically connected to the first penetration via, a power delivery network layer on a bottom surface of the substrate, and a first lower penetration via between the power delivery network layer and the first penetration via.

公开(公告)号：US20240128161A1

公开(公告)日：2024-04-18

申请号：US18379083

申请日：2023-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmoon Lee ,  Sangcheol Na ,  Sora You ,  Kyoungwoo Lee ,  Minchan Gwak ,  Youngwoo Kim ,  Jinkyu Kim ,  Seungmin Cha

IPC: H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/775 ,  H01L29/78696

Abstract: Provided is an integrated circuit device including a substrate, a plurality of semiconductor patterns on a first surface of the substrate, a gate electrode extending in a first direction and surrounding the semiconductor patterns, a source/drain region disposed on one side of the gate electrode, a vertical power wiring layer extending in a second direction, a liner structure including a first liner and a second liner, the first liner disposed on a lower portion of a sidewall of the vertical power wiring layer and including a first insulating material, and the second liner disposed on an upper portion of the sidewall of the vertical power wiring layer and including a second insulating material, a first contact disposed on the source/drain region and the vertical power wiring layer, and a back wiring structure disposed on a second surface of the substrate and electrically connected to the vertical power wiring layer.

公开(公告)号：US20230411471A1

公开(公告)日：2023-12-21

申请号：US18295867

申请日：2023-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungmin Cha ,  Minchan Gwak ,  Donghoon Hwang ,  Sora You ,  Sungmoon Lee

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/775 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/41766 ,  H01L27/088 ,  H01L29/775 ,  H01L29/42392 ,  H01L29/0673

Abstract: A semiconductor device includes first and second active regions on a substrate and extending in a first direction, first and second gate structures on the first and second active regions, respectively, the first and second gate structures extending in a second direction and being spaced apart from each other in the second direction, first and second source/drain regions on the first and second active regions, respectively, and spaced apart from the first and second gate structures, first and second contact plugs on the first and second source/drain regions and respectively connected to the first and second source/drain regions, and a vertical buried structure between the first and second gate structures and between the first and second source/drain regions. The vertical buried structure may include first and second side surfaces, and the first contact plug contacts the first side surface of the vertical buried structure.