公开(公告)号：US06366526B2

公开(公告)日：2002-04-02

申请号：US09790132

申请日：2001-02-21

申请人： Samuel D Naffziger ,  Donald R Weiss ,  John Wuu

发明人： Samuel D Naffziger ,  Donald R Weiss ,  John Wuu

IPC分类号： G11C800

CPC分类号： G11C8/10 ,  G11C11/418

摘要： A static random access memory (SRAM) cell is provided that optimizes the density of memory cells in an array with the maximum speed possible in addressing the memory cells for reading and writing operations. The SRAM cell is divided into groups of SRAM arrays of cells with a centrally located distributed global decoder to address any individual memory cell in the SRAM array. The global decoder accepts an addressing input and outputs a signal for selecting an individual column of memory cells in the SRAM array. The global decoder also outputs a signal selecting an individual row of memory cells contained in the SRAM array. The global decoder may include logic to decode addressing bits to produce a group select signal. Thus, the global decoder is able to select any single memory cell in the SRAM cell for reading or writing specific logical states.

摘要翻译： 提供了一种静态随机存取存储器（SRAM）单元，其以可能的最大速度来优化存储器单元的阵列密度，以便对存储单元进行寻址和写入操作。 SRAM单元被分成具有位于中心的分布式全局解码器的SRAM阵列阵列，以解决SRAM阵列中的任何单独的存储单元。 全局解码器接受寻址输入并输出用于选择SRAM阵列中存储单元的单独列的信号。 全局解码器还输出选择SRAM阵列中包含的各行存储单元的信号。 全局解码器可以包括用于解码寻址位以产生组选择信号的逻辑。 因此，全局解码器能够选择SRAM单元中的任何单个存储器单元用于读取或写入特定的逻辑状态。

公开(公告)号：US06243287B1

公开(公告)日：2001-06-05

申请号：US09492510

申请日：2000-01-27

申请人： Samuel D Naffziger ,  Donald R Weiss ,  John Wuu

发明人： Samuel D Naffziger ,  Donald R Weiss ,  John Wuu

IPC分类号： G11C1100

CPC分类号： G11C8/10 ,  G11C11/418

摘要： A static random access memory (SRAM) cell is provided that optimizes the density of memory cells in an array with the maximum speed possible in addressing the memory cells for reading and writing operations. The SRAM cell is divided into groups of SRAM arrays of cells with a centrally located distributed global decoder to address any individual memory cell in the SRAM array. The global decoder includes a first logic block that accepts addressing input and outputs a signal for selecting an individual column of memory cells in the SRAM array. The global decoder includes a second logic block that accepts addressing input and outputs a signal selecting an individual row of memory cells contained in the SRAM array. The global decoder may include a third logic block to decode addressing bits to produce a group select signal. Thus, the global decoder is able to select any signal memory cell in the SRAM cell for reading or writing specific logical states.

摘要翻译： 提供了一种静态随机存取存储器（SRAM）单元，其以阵列中的存储器单元的密度优化，以最大速度寻址存储器单元以进行读取和写入操作。 SRAM单元被分成具有位于中心的分布式全局解码器的SRAM阵列阵列，以解决SRAM阵列中的任何单独的存储单元。 全局解码器包括第一逻辑块，其接受寻址输入并输出用于选择SRAM阵列中的存储单元的单独列的信号。 全局解码器包括第二逻辑块，其接受寻址输入并输出选择SRAM阵列中包含的各行存储单元的信号。 全局解码器可以包括用于解码寻址位以产生组选择信号的第三逻辑块。 因此，全局解码器能够选择SRAM单元中的任何信号存储单元用于读取或写入特定的逻辑状态。

公开(公告)号：US06493855B1

公开(公告)日：2002-12-10

申请号：US09507498

申请日：2000-02-18

申请人： Donald R Weiss ,  Samuel D Naffziger

发明人： Donald R Weiss ,  Samuel D Naffziger

IPC分类号： G06F1750

CPC分类号： G06F12/0893

摘要： A system and method which implement a memory component of an integrated circuit as multiple, relatively small sub-arrays of memory to enable great flexibility in organizing memory within the integrated circuit are provided. In a preferred embodiment, the memory component of an integrated circuit is implemented as multiple, relatively small sub-arrays of memory, which enable a designer great flexibility in arranging such sub-arrays within an integrated circuit. Also, in a preferred embodiment, the memory component of an integrated circuit is implemented as multiple memory sub-arrays that are each independent. For example, in a preferred embodiment, each memory sub-array comprises its own decode circuitry for decoding memory addresses that are being requested to be accessed by an instruction, and each memory sub-array comprises its own I/O circuitry. In one implementation of a preferred embodiment, each of the independent memory sub-arrays implemented in an integrated circuit comprises no more than approximately five percent of the total memory implemented on the integrated circuit. In another implementation, each of the independent memory sub-arrays on an integrated circuit is no larger than approximately the average size of other non-memory components implemented on the integrated circuit. Additionally, in further implementation, the memory component of an integrated circuit comprises at least a 20 independent memory sub-arrays. Therefore, in a preferred embodiment, each independent sub-array is relatively small in size to enable great flexibility in organizing the memory on an integrated circuit. Furthermore, because each sub-array is independent, greater flexibility is available in repairing defects through redundancy.

摘要翻译： 提供了一种实现集成电路的存储器组件作为多个相对较小的存储器子阵列以使集成电路内组织存储器的极大灵活性的系统和方法。 在优选实施例中，集成电路的存储器部件被实现为多个相对较小的存储器子阵列，这使得设计人员能够在集成电路内布置这样的子阵列时具有很大的灵活性。 此外，在优选实施例中，集成电路的存储器组件被实现为各自独立的多个存储器子阵列。 例如，在优选实施例中，每个存储器子阵列包括其自身的解码电路，用于解码正被请求由指令访问的存储器地址，并且每个存储器子阵列包括其自己的I / O电路。 在优选实施例的一个实现中，在集成电路中实现的每个独立存储器子阵列包括不超过在集成电路上实现的总存储器的大约百分之五。 在另一实现中，集成电路上的每个独立存储器子阵列不大于在集成电路上实现的其他非存储器组件的平均大小。 另外，在进一步的实现中，集成电路的存储器组件包括至少20个独立的存储器子阵列。 因此，在优选实施例中，每个独立的子阵列的尺寸相对较小，以便在集成电路上组织存储器方面具有极大的灵活性。 此外，由于每个子阵列是独立的，因此通过冗余修复缺陷可提供更大的灵活性。

公开(公告)号：US06192001B1

公开(公告)日：2001-02-20

申请号：US09510287

申请日：2000-02-21

申请人： Donald R Weiss ,  John Wuu ,  Reid James Riedlinger

发明人： Donald R Weiss ,  John Wuu ,  Reid James Riedlinger

IPC分类号： G11C810

CPC分类号： G11C11/419

摘要： The present invention integrates a WWTM circuit with the write driver circuitry, which is an inherent part of any conventional SRAM design. Thus, a circuit for writing data into and weak write testing a memory cell is provided. In one embodiment, the circuit comprises a write driver that has an output for applying a write or a weak write output signal at the memory cell. The write driver has first and second selectable operating modes. In the first mode, the write driver is set to apply a weak write output signal from the output for performing a weak write test on the cell. In the second mode, the write driver is set to apply a normal write output signal that is sufficiently strong for writing a data value into the cell when it is healthy.

摘要翻译： 本发明将WWTM电路与写驱动器电路集成，该驱动器电路是任何常规SRAM设计的固有部分。 因此，提供了用于将数据写入并弱写入测试存储器单元的电路。 在一个实施例中，电路包括具有用于在存储器单元处施加写入或弱写入输出信号的输出的写入驱动器。 写驱动器具有第一和第二可选操作模式。 在第一模式中，写入驱动器被设置为从输出端施加弱写入输出信号，以对单元执行弱写入测试。 在第二模式中，写入驱动器被设置为施加足够强的正常写入输出信号，以便当数据值健康时将数据值写入单元。

公开(公告)号：US06208565B1

公开(公告)日：2001-03-27

申请号：US09507333

申请日：2000-02-18

申请人： Reid James Riedlinger ,  Donald R Weiss

发明人： Reid James Riedlinger ,  Donald R Weiss

IPC分类号： G11C700

CPC分类号： G11C8/16

摘要： A system and method are disclosed which provide a pulse write mechanism to enable a port to write to a register structure without requiring a large amount of circuitry. One or more ports may be coupled to a register structure in a manner that enables the ports to write data to the register structure without requiring a large amount of circuitry. The ports may be coupled to the register structure in a manner that enables them the capability of reading data from the register structure without requiring additional circuitry beyond that required for a write operation. A preferred embodiment implements a single-ended write structure, wherein a data carrier (e.g., BIT line) is utilized to carry a data value desired to be written for a port. A preferred embodiment comprises a write pulse mechanism, such as a NFET, capable of setting the memory cell to an initial value before performing a write thereto. Before performing a write operation to a memory cell, the write pulse signal is fired causing the write pulse mechanism to initialize the memory cell to a high voltage value. If the value of the BIT line is the same as the value to which the memory cell was initialized, the memory access mechanism enables the memory cell to remain at such value. However, if the value of the BIT line is different than the initial value of the memory cell, the memory access mechanism transitions the memory cell to the value of the BIT line.

摘要翻译： 公开了一种提供脉冲写入机制以使端口能够写入寄存器结构而不需要大量电路的系统和方法。 一个或多个端口可以以使得端口能够将数据写入寄存器结构而不需要大量电路的方式耦合到寄存器结构。 端口可以​​以使得它们能够从寄存器结构读取数据的能力而不需要超出写入操作所需的额外电路的方式耦合到寄存器结构。 优选实施例实现单端写入结构，其中使用数据载体（例如，BIT线）来承载期望为端口写入的数据值。 优选实施例包括能够在执行写入之前将存储器单元设置为初始值的写入脉冲机制，例如NFET。 在对存储单元执行写入操作之前，写入脉冲信号被触发，使得写入脉冲机制将存储单元初始化为高电压值。 如果BIT行的值与存储单元初始化的值相同，则存储器访问机制使存储单元保持在这样的值。 但是，如果BIT行的值与存储单元的初始值不同，则存储器访问机制将存储单元转换为BIT行的值。

公开(公告)号：US06292093B1

公开(公告)日：2001-09-18

申请号：US09507862

申请日：2000-02-22

申请人： Shyang-Tai Su ,  Donald R Weiss

发明人： Shyang-Tai Su ,  Donald R Weiss

IPC分类号： G05B100

CPC分类号： G06F7/02

摘要： A circuit for signalling if any like ordered bits Ak and Bk in first and second binary words differ comprises a comparator for each pair of like ordered bits and a common terminal. Each comparator includes first and second FETs arranged so: (a) the first and second levels of Ak are coupled to the common terminal via the first FET in response to Bk having the first value, (b) the first and second levels of Bk are coupled to the common terminal via the second FET in response to Ak having the first value, (c) the first FET decouples Ak from the common terminal and tends to cause the common terminal to be at the second level in response to Bk having the second value, (d) the second FET decouples Bk from the common terminal and tends to cause the common terminal to be at the second level in response to Ak having the second value, and (e) the common terminal is at the second level only in response to Ak Bk. A FET connected as a diode and coupled between the common terminal and each of the FETs maintains the common terminal at the second value in response to Ai Bi, where i is any value of k.

摘要翻译： 在第一和第二二进制字中有任何类似有序位Ak和Bk不同的用于发信号的电路包括用于每对相似有序位和公共端的比较器。 每个比较器包括第一和第二FET，其布置为：（a）第一和第二电平的Ak响应于具有第一值的B k经由第一FET耦合到公共端子，（b）Bk的第一和第二电平 响应于具有第一值的Ak，经由第二FET耦合到公共端子，（c）第一FET将Ak与公共端子分离，并且倾向于使公共端子响应于具有第二值的B k而处于第二电平 值，（d）第二FET将Bk与公共端分离，并且倾向于使公共端响应具有第二值的Ak而处于第二电平，以及（e）仅在公共端 响应Ak Bk。 作为二极管连接并连接在公共端子和每个FET之间的FET，响应于“自定义字符”=“US06292093-20010918-P00900.TIF”ID =“CUSTOM-CHARACTER”将公共端子维持在第二值 -00002“> Bi，其中i是k的任何值。

公开(公告)号：US06226217B1

公开(公告)日：2001-05-01

申请号：US09507207

申请日：2000-02-18

申请人： Reid James Riedlinger ,  Donald R Weiss

发明人： Reid James Riedlinger ,  Donald R Weiss

IPC分类号： G11C800

CPC分类号： G11C11/412

摘要： A system and method are disclosed which provide a register structure enabling a dual-ended write thereto with a minimum amount of high-level metal tracks and components, thereby minimizing the amount of surface area required for such register structure. A data carrier (e.g., a BIT line) is utilized to carry a data value desired to be written from a port to a memory cell of a register structure. Such a data carrier may be implemented as a high-level metal track that spans multiple register structures to enable a port the capability of writing to such multiple register structures. Also, a line for triggering a write operation for a port (e.g., a WORD line) is implemented, and such a triggering line may be implemented as a high-level metal track. A preferred embodiment provides a register structure that includes a dual-ended write mechanism. In a preferred embodiment, a complementary data carrier for a port is generated locally within a register structure. Thus, a preferred embodiment minimizes the number of high-level metal tracks required because a complementary data carrier for each port is not required to be implemented as a high-level metal track. Furthermore, a preferred embodiment generates a complementary data carrier for a port locally within the register structure in a manner that does not require an inverter. More specifically, a preferred embodiment implements a NFET that is arranged in a manner to generate the necessary complementary data carrier (e.g., NBIT line) for performing a dual-ended write.

摘要翻译： 公开了一种系统和方法，其提供了一种寄存器结构，其能够以最小量的高级金属轨道和部件实现双端写入，从而最小化这种寄存器结构所需的表面积的量。 使用数据载体（例如，BIT线）将希望从端口写入的数据值传送到寄存器结构的存储单元。 这样的数据载体可以实现为跨越多个寄存器结构的高级金属轨道，以使端口能够写入这样的多个寄存器结构。 而且，实现用于触发端口（例如，WORD线）的写操作的线，并且这样的触发线可以被实现为高级金属轨道。 优选实施例提供包括双端写机构的寄存器结构。 在优选实施例中，用于端口的互补数据载体在寄存器结构内本地生成。 因此，优选实施例使得需要的高级金属轨道的数量最小化，因为用于每个端口的互补数据载体不需要被实现为高级金属轨道。 此外，优选实施例以不需要逆变器的方式在寄存器结构内本地生成用于端口的互补数据载体。 更具体地，优选实施例实施NFET，其以以生成用于执行双端写入的必要的互补数据载体（例如，NBIT线）的方式被布置。

公开(公告)号：US07076376B1

公开(公告)日：2006-07-11

申请号：US11024086

申请日：2004-12-28

申请人： Donald R Weiss ,  Richard L. Woodruff ,  John J. Wuu

发明人： Donald R Weiss ,  Richard L. Woodruff ,  John J. Wuu

IPC分类号： G11C29/04

CPC分类号： G11C29/028 ,  G11C11/41 ,  G11C11/419 ,  G11C29/24 ,  G11C29/50 ,  G11C2029/5006

摘要： According to at least one embodiment, a method comprises measuring drive current of a reference memory cell of a circuit, and determining, based on the measured drive current of the reference memory cell, a drive current to be supplied to a calibration memory cell of the circuit to mimic a defective memory cell. The method further comprises supplying the determined drive current to the calibration memory cell, and using the calibration memory cell to determine strength of a weak write to be utilized by a weak write test for detecting defective memory cells.

摘要翻译： 根据至少一个实施例，一种方法包括测量电路的参考存储单元的驱动电流，以及基于所测量的参考存储单元的驱动电流来确定要提供给该参考存储单元的校准存储单元的驱动电流 电路以模拟有缺陷的存储器单元。 该方法还包括将确定的驱动电流提供给校准存储单元，以及使用校准存储单元来确定弱写入测试用于检测有缺陷的存储器单元的弱写入的强度。

公开(公告)号：US06249465B1

公开(公告)日：2001-06-19

申请号：US09506620

申请日：2000-02-18

申请人： Donald R Weiss ,  Jay Fleischman ,  Jeffery C Brauch

发明人： Donald R Weiss ,  Jay Fleischman ,  Jeffery C Brauch

IPC分类号： G11C700

CPC分类号： G11C29/802 ,  G11C29/848

摘要： A system and method are disclosed which provide the capability of repairing an optimum number of defective memory segments, such as RAM segments, in order to minimize the amount of unused repairing circuitry, such as fuses used for repairing defects within the memory. A preferred embodiment of the present invention provides a RAM block implemented such that the number of fuses required for repairing defects therein is proportional to the optimum number of defective segments capable of being repaired. A preferred embodiment allows for repairing an optimum number of defective segments, while being capable of repairing any of the segments (up to the optimum number) by mapping repair data to an appropriate defective segment. A preferred embodiment provides a repairable RAM block comprising multiple segments of RAM memory cells that are each repairable, a state machine capable of generating repair data for repairing one or more defective segments, a scan address machine capable of generating data identifying one or more defective segments, and a mapping circuitry for mapping the generated repair data of the state machine to the one or more defective segments specified by the scan address machine. Accordingly, by providing the capability of mapping generated repair data to any one of the segments of RAM that is detected as being defective, a preferred embodiment enables repairing an optimum number of defective segments, without being required to provide sufficient circuitry for repairing every segment of RAM.

摘要翻译： 公开了一种系统和方法，其提供修复最佳数量的缺陷存储器段（例如RAM段）的能力，以便最小化未使用的修复电路的量，例如用于修复存储器内的缺陷的熔丝。 本发明的优选实施例提供一种实现的RAM块，使得修复其中的缺陷所需的熔丝数量与能够被修复的缺陷段的最佳数量成比例。 优选实施例允许修复最佳数量的缺陷段，同时能够通过将修复数据映射到适当的缺陷段来修复任何段（达到最佳数目）。 优选实施例提供了一种可修复的RAM块，其包括可修复的多个RAM存储器单元段，能够产生用于修复一个或多个缺陷段的修复数据的状态机，能够产生标识一个或多个缺陷段的数据的扫描地址机 以及映射电路，用于将所生成的状态机的修复数据映射到由扫描地址机指定的一个或多个缺陷段。 因此，通过提供将生成的修复数据映射到被检测为有缺陷的RAM的任何一个片段的能力，优选实施例能够修复最佳数量的有缺陷的段，而不需要提供足够的电路来修复每个段的 随机存取存储器。