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公开(公告)号：US11935599B2
公开(公告)日：2024-03-19
申请号：US17725911
申请日：2022-04-21
CPC分类号： G11C16/102 , G11C7/1051 , G11C16/08 , G11C16/24 , G11C16/26
摘要： A fast burst program sequence that reduces overall NAND flash programming time is disclosed. The burst program sequence includes maintaining a charge pump in an ON state and not fully discharging the WL/BLs at the conclusion of the programming phase of each program operation. As a result, the fast burst program sequence provides total program time savings over an existing cache program sequence by eliminating the full WL/BL discharge and charge pump reset that conventionally occurs after each program operation, which in turn, allows for the transfer of next page data from the page buffer to the data latches to be hidden within the program time of a prior/current program operation.
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公开(公告)号：US20240221803A1
公开(公告)日：2024-07-04
申请号：US18360273
申请日：2023-07-27
发明人： Hua-Ling Cynthia Hsu , Victor Avila , Henry Chin
IPC分类号： G11C7/10
CPC分类号： G11C7/1096 , G11C7/106 , G11C7/1069
摘要： An apparatus includes control circuits configured to connect to a plurality of non-volatile memory cells. The control circuits are configured to receive a read command directed to at least one logical page of data during a program operation to store the at least one logical page of data in a plurality of non-volatile memory cells. The control circuits are further configured to stop the program operation at an intermediate stage of programming, read the plurality of non-volatile memory cells at the intermediate stage to obtain first partial data of at least one logical page and obtain the at least one logical page of data by combining the first partial data with second partial data of the at least one logical page stored in data latches.
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