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公开(公告)号：US07746140B2
公开(公告)日：2010-06-29
申请号：US11550997
申请日：2006-10-19
CPC分类号： H03K3/356113 , G01R31/318541
摘要： A scannable latch is disclosed. The scannable latch includes a dynamic circuit, two cross-coupled NAND gates coupled to the dynamic circuit, and a pair of stacked transistors coupled to the dynamic circuit. One of the stacked transistors is for receiving data signals, and the other stacked transistors is for receiving scan in signals.
摘要翻译： 公开了可扫描的闩锁。 可扫描锁存器包括动态电路，耦合到动态电路的两个交叉耦合NAND门和耦合到动态电路的一对堆叠晶体管。 堆叠晶体管中的一个用于接收数据信号，而另一个堆叠晶体管用于接收扫描信号。
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公开(公告)号：US07170328B2
公开(公告)日：2007-01-30
申请号：US10982112
申请日：2004-11-05
CPC分类号： H03K3/356113 , G01R31/318541
摘要： A scannable latch is disclosed. The scannable latch includes a dynamic circuit, two cross-coupled NAND gates coupled to the dynamic circuit, and a pair of stacked transistors coupled to the dynamic circuit. One of the stacked transistors is for receiving data signals, and the other stacked transistors is for receiving scan in signals.
摘要翻译： 公开了可扫描的闩锁。 可扫描锁存器包括动态电路，耦合到动态电路的两个交叉耦合NAND门和耦合到动态电路的一对堆叠晶体管。 堆叠晶体管中的一个用于接收数据信号，而另一个堆叠晶体管用于接收扫描信号。
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公开(公告)号：US07170316B2
公开(公告)日：2007-01-30
申请号：US10982018
申请日：2004-11-05
IPC分类号： H03K19/177 , G06F7/38
CPC分类号： H03K19/1772
摘要： A programmable logic array (PLA) latch is disclosed. The PLA latch includes a first logic array, a second logic array and only one output latch. The second logic array is coupled to the first logic array. The output latch is coupled to the second logic array.
摘要翻译： 公开了一种可编程逻辑阵列（PLA）锁存器。 PLA锁存器包括第一逻辑阵列，第二逻辑阵列和仅一个输出锁存器。 第二逻辑阵列耦合到第一逻辑阵列。 输出锁存器耦合到第二逻辑阵列。
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4.发明授权公开(公告)号：US07710796B2
公开(公告)日：2010-05-04
申请号：US11935741
申请日：2007-11-06
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C11/418
摘要： A circuit and method includes first circuits powered by a first supply voltage and second circuits powered by a second supply voltage. A level shifter is coupled between the first circuits and the second circuits. The level shifter is configured to select a supply voltage output for a circuit including one of the first supply voltage and the second supply voltage in accordance an input signal, where the input signal depends on at least one of an operation to be performed and component performing the operation.
摘要翻译： 电路和方法包括由第一电源电压供电的第一电路和由第二电源电压供电的第二电路。 电平移位器耦合在第一电路和第二电路之间。 电平移位器被配置为根据输入信号选择包括第一电源电压和第二电源电压中的一个的电路的电源电压输出，其中输入信号取决于要执行的操作和组件执行中的至少一个 的操作。
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5.发明申请公开(公告)号：US20080189670A1
公开(公告)日：2008-08-07
申请号：US12060768
申请日：2008-04-01
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block and then performing logic synthesis for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit is produced, the circuit design method includes eliminating unnecessary devices from the intermediate circuit to produce a final logic circuit, and then sizing the devices in the final circuit to complete the design.
摘要翻译： 可用于逻辑合成的电路库限于单个动态电路块或逻辑合成块。 电路设计方法包括首先定义逻辑合成块，然后执行用于要实现的预定逻辑运算的逻辑合成。 限制到单个逻辑合成块的逻辑合成步骤产生中间电路设计，其必然包括一系列动态电路块，每个动态电路块与单个复位信号相关联。 一旦生成了中间电路，电路设计方法包括从中间电路中消除不必要的设备，产生最终的逻辑电路，然后对最终电路中的器件进行尺寸调整以完成设计。
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6.发明授权公开(公告)号：US07363609B2
公开(公告)日：2008-04-22
申请号：US09915437
申请日：2001-07-26
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block (16) and then performing logic synthesis (17) for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design (29) which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit (29) is produced, the circuit design method includes eliminating unnecessary devices (46) from the intermediate circuit (29) to produce a final logic circuit, and then sizing the devices (48) in the final circuit to complete the design.
摘要翻译： 可用于逻辑合成的电路库限于单个动态电路块或逻辑合成块。 电路设计方法包括首先定义逻辑合成块（16），然后执行用于要实现的预定逻辑运算的逻辑合成（17）。 限制到单个逻辑合成块的逻辑合成步骤产生中间电路设计（29），其必须包括一系列与单个复位信号相关联的动态电路块。 一旦产生中间电路（29），电路设计方法包括从中间电路（29）消除不必要的装置（46）以产生最终的逻辑电路，然后对最终电路中的装置（48）进行尺寸调整以完成 设计。
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公开(公告)号：US07165006B2
公开(公告)日：2007-01-16
申请号：US10976259
申请日：2004-10-28
申请人： Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi , James Douglas Warnock , Dieter Wendel
发明人： Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi , James Douglas Warnock , Dieter Wendel
IPC分类号： G06F19/00
CPC分类号： G06F1/3203 , G06F1/325
摘要： An apparatus, a method and a computer program product are provided for conserving energy during functional mode of a processor by disabling the scan chain. By inserting logic gating into the scan chain it is possible to disable the scan chain during the processor's functional mode. During functional mode the scan out port of the latch bit in a scan chain toggles, which leads to unnecessary energy consumption. By gating scan control signals and the scan out port of a latch bit, the scan chain segment between latch bits can be disconnected. Therefore, the scan control signals can disable the scan chain during functional mode.
摘要翻译： 提供了一种装置，方法和计算机程序产品，用于通过禁用扫描链来在处理器的功能模式期间节省能量。 通过将逻辑门控插入到扫描链中，可以在处理器的功能模式期间禁用扫描链。 在功能模式期间，扫描链中锁存位的扫描输出端口切换，这导致不必要的能量消耗。 通过门控扫描控制信号和锁存位的扫描输出端口，可以断开锁存位之间的扫描链段。 因此，扫描控制信号可以在功能模式下禁用扫描链。
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公开(公告)号：US06535041B1
公开(公告)日：2003-03-18
申请号：US10093440
申请日：2002-03-07
申请人： Robert John Bucki , Sang Hoo Dhong , Jeffrey Herbert Fischer , Joel Abraham Silberman , Osamu Takahashi
发明人： Robert John Bucki , Sang Hoo Dhong , Jeffrey Herbert Fischer , Joel Abraham Silberman , Osamu Takahashi
IPC分类号： H03K312
CPC分类号： H03K3/356113 , H03K3/012 , H03K3/013
摘要： A dynamic node keeper device for a dynamic strobe circuit is controlled by the signal at the intermediate node, that is, the signal at the output of the strobe component. By controlling the dynamic node keeper device through the strobe component output, the keeper device is active or conductive only when necessary to protect against noises in the pull down network for the strobe circuit. At all other times in the course of operation of the dynamic strobe circuit, the dynamic node keeper device according to the invention is nonconductive or inactive. Thus, the dynamic strobe circuit according to the invention reduces power consumption.
摘要翻译： 用于动态选通电路的动态节点保持器装置由中间节点处的信号，即选通组件输出端的信号控制。 通过通过选通分量输出来控制动态节点保持器装置，只有在必要时保持装置才有效或不导通，以防止用于选通电路的下拉网络中的噪声。 在动态频闪电路的操作过程中的所有其他时间，根据本发明的动态节点保持装置是不导通或不活动的。 因此，根据本发明的动态选通电路降低功耗。
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9.发明授权Cycle control circuit for extending a cycle period of a dynamic memory device subarray 失效循环控制电路，用于延长动态存储器件子阵列的周期周期公开(公告)号：US06175535B1
公开(公告)日：2001-01-16
申请号：US09490405
申请日：2000-01-24
申请人： Sang Hoo Dhong , Manabu Ohkubo , Shohji Onishi , Osamu Takahashi
发明人： Sang Hoo Dhong , Manabu Ohkubo , Shohji Onishi , Osamu Takahashi
IPC分类号： G11C800
摘要： A cycle control circuit for use with a memory device subarray and method of operation thereof. The cycle control circuit includes a previous address buffer for storing a last accessed address of the subarray and an address comparator for comparing a current requested address with the last accessed address in the previous address buffer. The cycle control circuit also includes a cycle counter, coupled to the address comparator, that receives a control signal generated by the address comparator and, in response thereto, modifies a reset operation of the subarray. In another aspect, the method includes applying an address to the subarray and generating control signals for the subarray to produce a data output in response to the address. After producing the data output, the applied address is stored. Next, a new address is received and the new address is compared to the stored address. In response to the stored and new addresses being the same, the reset operation of the subarray is modified to again generate the data output in a shorter period of time.
摘要翻译： 一种与存储器件子阵列一起使用的循环控制电路及其操作方法。 周期控制电路包括用于存储子阵列的最后访问地址的先前地址缓冲器和用于将当前请求地址与先前地址缓冲器中的最后访问地址进行比较的地址比较器。 循环控制电路还包括耦合到地址比较器的周期计数器，其接收由地址比较器产生的控制信号，并响应于此，修改子阵列的复位操作。 在另一方面，该方法包括将地址应用于子阵列，并产生用于子阵列的控制信号以产生响应于该地址的数据输出。 产生数据输出后，存储应用的地址。 接下来，接收到新地址，并将新地址与存储的地址进行比较。 响应于存储的和新的地址相同，子阵列的复位操作被修改以在更短的时间段内再次产生数据输出。
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公开(公告)号：US5771268A
公开(公告)日：1998-06-23
申请号：US762910
申请日：1996-12-10
CPC分类号： G11C19/38
摘要： A high-speed rotator array for shifting input data a specified amount. The rotator array includes a plurality of straight shift control lines extending across the array for receiving shift data representative of shift values, and a plurality of input terminals for receiving input data to be shifted. The rotator array also includes a plurality of data lines coupled to the plurality of input terminals that extend both diagonally and horizontally across the array. In response to the rotator array receiving the shift data and the input data, a plurality of output terminals transmit the shifted output data.
摘要翻译： 用于将输入数据移位一定量的高速旋转器阵列。 旋转器阵列包括跨越阵列延伸的多个直移位控制线，用于接收代表移位值的移位数据，以及多个用于接收要移位的输入数据的输入端。 旋转器阵列还包括耦合到多个输入端子的多条数据线，跨越阵列沿对角线和水平方向延伸。 响应于接收到移位数据和输入数据的旋转体阵列，多个输出端子发送移位的输出数据。
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