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    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    1.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME 审中-公开
    半导体存储器件及其操作方法

    公开(公告)号：US20130163345A1

    公开(公告)日：2013-06-27

    申请号：US13605552

    申请日：2012-09-06

    申请人： Sang Tae AHN ,  Gyu Seog Cho ,  Chae Moon Lim ,  Yoo Nam Jeon ,  Seung Hwan Baik ,  Hee Jin Lee ,  Jae Seok Kim ,  Kyung Sik Mun ,  U Seon Im

    发明人： Sang Tae AHN ,  Gyu Seog Cho ,  Chae Moon Lim ,  Yoo Nam Jeon ,  Seung Hwan Baik ,  Hee Jin Lee ,  Jae Seok Kim ,  Kyung Sik Mun ,  U Seon Im

    IPC分类号： G11C16/12 ,  G11C16/04

    CPC分类号： G11C16/0483 ,  G11C16/12 ,  G11C16/3427

    摘要： A method of operating a semiconductor memory device includes an operation of applying a first voltage to selected bit lines, a second voltage to unselected bit lines and a common source line, and turning on drain and source selection transistors, an operation of applying a program voltage to a selected word line and a switch voltage to a switch word line, and applying a first pass voltage to first unselected word lines disposed between the switch word line and a common source line and between the selected word line and a bit line, and elevating the switch voltage to generate hot electrons and inject the hot electrons to a selected memory cell of the selected word line to program the selected cell.

    摘要翻译： 一种操作半导体存储器件的方法包括：将第一电压施加到所选择的位线，将第二电压施加到未选定位线和公共源极线，以及接通漏极和源极选择晶体管的操作，施加编程电压 将选择的字线和开关电压切换到开关字线，并且将第一通过电压施加到设置在开关字线和公共源极线之间以及所选择的字线和位线之间的第一未选择字线，并且升高 所述开关电压产生热电子并将热电子注入到所选择的字线的选定的存储单元中以对所选择的单元进行编程。

    Recess channel transistor for preventing deterioration of device characteristics due to misalignment of gate layers and method of forming the same
    2.
    发明授权
    Recess channel transistor for preventing deterioration of device characteristics due to misalignment of gate layers and method of forming the same 失效
    用于防止由于栅极层的不对准导致的器件特性劣化的凹陷沟道晶体管及其形成方法

    公开(公告)号：US07482230B2

    公开(公告)日：2009-01-27

    申请号：US12020686

    申请日：2008-01-28

    申请人： Gyu Seog Cho ,  Yong Taik Kim

    发明人： Gyu Seog Cho ,  Yong Taik Kim

    IPC分类号： H01L21/335

    CPC分类号： H01L21/823425 ,  H01L21/823412 ,  H01L21/823437 ,  H01L29/66621

    摘要： The recess channel transistor includes: a semiconductor substrate including a device insulation layer defining an activation region in which recesses are formed; insulation buffer patterns, each of which is formed at an opening of the recess on a surface of the substrate; gates, each of which includes a recess gate formed in the recess and a top gate formed on the substrate; spacers, each of which is formed at both sides of the gate; and a source region and a drain region formed at both sides of each gate on the surface of the substrate, where the source and drain regions have an even doping profile due to the existence of insulation buffer patterns. Accordingly, characteristics of the transistor can be prevented from deteriorating due to misalignment of the top gate with the recess gate.

    摘要翻译： 所述凹槽通道晶体管包括：半导体衬底，其包括限定形成有凹部的激活区域的器件绝缘层; 绝缘缓冲图案，其各自形成在基板的表面上的凹部的开口处; 栅极，每个栅极包括形成在凹部中的凹槽和形成在衬底上的顶栅; 间隔件，每个间隔件形成在门的两侧; 以及源极区和漏极区，形成在衬底表面上的每个栅极的两侧，其中由于存在绝缘缓冲图案，源区和漏区具有均匀的掺杂分布。 因此，可以防止晶体管的特性由于顶栅与凹槽的不对准而劣化。

    Method of forming a transistor in a semiconductor device
    4.
    发明授权
    Method of forming a transistor in a semiconductor device 失效
    在半导体器件中形成晶体管的方法

    公开(公告)号：US06492246B1

    公开(公告)日：2002-12-10

    申请号：US09708510

    申请日：2000-11-09

    申请人： Gyu Seog Cho ,  Kyung Wook Park

    发明人： Gyu Seog Cho ,  Kyung Wook Park

    IPC分类号： H01L2100

    CPC分类号： H01L29/78696 ,  H01L21/26533 ,  H01L29/66772 ,  H01L29/78603

    摘要： There is disclosed a method of manufacturing a transistor in a semiconductor device. The present invention isolates a semiconductor substrate by an oxide layer with only a source, a drain and a channel region necessary for driving a transistor being left. Thus, it can obviate the current components due to parasitic factors to improve the punch-through characteristic.

    摘要翻译： 公开了一种在半导体器件中制造晶体管的方法。 本发明仅通过氧化层隔离半导体衬底，只有源极，漏极和驱动晶体管所需的沟道区。 因此，由于寄生因素可以消除电流分量，从而提高穿透特性。

    Semiconductor memory device and method for fabricating the same
    5.
    发明授权
    Semiconductor memory device and method for fabricating the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US06320227B1

    公开(公告)日：2001-11-20

    申请号：US09471076

    申请日：1999-12-22

    申请人： Jong Wook Lee ,  Gyu Seog Cho

    发明人： Jong Wook Lee ,  Gyu Seog Cho

    IPC分类号： H01L2701

    CPC分类号： H01L27/1203 ,  H01L27/1082

    摘要： A semiconductor memory device using a silicon-on-insulator device, including a semiconductor memory device capable of reducing the topology between a cell region and a peripheral region and preventing floating body effect.

    摘要翻译： 一种使用绝缘体上硅器件的半导体存储器件，包括能够减小单元区域与外围区域之间的拓扑并防止浮体效应的半导体存储器件。

    Semiconductor memory device and method for fabricating the same
    6.
    发明授权
    Semiconductor memory device and method for fabricating the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US06429074B2

    公开(公告)日：2002-08-06

    申请号：US09964420

    申请日：2001-09-28

    申请人： Jong Wook Lee ,  Gyu Seog Cho

    发明人： Jong Wook Lee ,  Gyu Seog Cho

    IPC分类号： H01L21336

    CPC分类号： H01L27/1203 ,  H01L27/1082

    摘要： A method for fabricating a semiconductor memory device using a silicon-on-insulator device, including forming a semiconductor memory device capable of reducing the topology between a cell region and a peripheral region and preventing floating body effect.

    摘要翻译： 一种使用绝缘体上硅器件制造半导体存储器件的方法，包括形成能够减小单元区域与周边区域之间的拓扑结构并防止浮体效应的半导体存储器件。

    Manufacturing method of transistor structure having a recessed channel
    8.
    发明授权
    Manufacturing method of transistor structure having a recessed channel 有权
    具有凹陷通道的晶体管结构的制造方法

    公开(公告)号：US08658491B2

    公开(公告)日：2014-02-25

    申请号：US12890926

    申请日：2010-09-27

    申请人： Gyu Seog Cho

    发明人： Gyu Seog Cho

    IPC分类号： H01L21/8234

    CPC分类号： H01L29/66621 ,  H01L21/823437 ,  H01L29/66606 ,  H01L29/7834

    摘要： A semiconductor device and a method for manufacturing the same are disclosed. The disclosed semiconductor device includes a semiconductor substrate having a device isolation structure for delimiting an active region, the active region being recessed and grooves being defined in channel forming areas of the active region; gates formed in and over the grooves; gate spacers formed on both sidewalls of the gates over portions of the recessed active region which are positioned on both sides of the gates; an LDD region formed in the active region under the gate spacers; junction areas formed in the active region on both sides of the gates including the gate spacers; and landing plugs formed on the junction areas.

    摘要翻译： 公开了一种半导体器件及其制造方法。 所公开的半导体器件包括具有用于限定有源区的器件隔离结构的半导体衬底，有源区是凹陷的，并且沟槽限定在有源区的沟道形成区中; 形成在槽内和上面的门; 栅极隔离物在位于栅极两侧的凹入有源区的部分上形成在栅极的两个侧壁上; 形成在栅极间隔下的有源区中的LDD区; 形成在包括栅极间隔物的栅极两侧的有源区域中的接合区域; 并在接合区域上形成着陆塞。

    Semiconductor device with recessed active region and gate in a groove
    9.
    发明授权
    Semiconductor device with recessed active region and gate in a groove 有权
    半导体器件具有凹入的有源区和栅极在沟槽中

    公开(公告)号：US07825464B2

    公开(公告)日：2010-11-02

    申请号：US12020651

    申请日：2008-01-28

    申请人： Gyu Seog Cho

    发明人： Gyu Seog Cho

    IPC分类号： H01L29/78

    CPC分类号： H01L29/66621 ,  H01L21/823437 ,  H01L29/66606 ,  H01L29/7834

    摘要： A semiconductor device and a method for manufacturing the same are disclosed. The disclosed semiconductor device includes a semiconductor substrate having a device isolation structure for delimiting an active region, the active region being recessed and grooves being defined in channel forming areas of the active region; gates formed in and over the grooves; gate spacers formed on both sidewalls of the gates over portions of the recessed active region which are positioned on both sides of the gates; an LDD region formed in the active region under the gate spacers; junction areas formed in the active region on both sides of the gates including the gate spacers; and landing plugs formed on the junction areas.

    摘要翻译： 公开了一种半导体器件及其制造方法。 所公开的半导体器件包括具有用于限定有源区的器件隔离结构的半导体衬底，有源区是凹陷的，并且沟槽限定在有源区的沟道形成区中; 形成在槽内和上面的门; 栅极隔离物在位于栅极两侧的凹入有源区的部分上形成在栅极的两个侧壁上; 形成在栅极间隔下的有源区中的LDD区; 形成在包括栅极间隔物的栅极两侧的有源区域中的接合区域; 和在连接区域上形成的着陆塞。

    Recess channel transistor for preventing deterioration of device characteristics due to misalignment of gate layers and method of forming the same
    10.
    发明申请
    Recess channel transistor for preventing deterioration of device characteristics due to misalignment of gate layers and method of forming the same 审中-公开
    用于防止由于栅极层的不对准导致的器件特性劣化的凹陷沟道晶体管及其形成方法

    公开(公告)号：US20070090452A1

    公开(公告)日：2007-04-26

    申请号：US11299544

    申请日：2005-12-12

    申请人： Gyu Seog Cho ,  Yong Taik Kim

    发明人： Gyu Seog Cho ,  Yong Taik Kim

    IPC分类号： H01L21/336 ,  H01L29/94

    CPC分类号： H01L21/823425 ,  H01L21/823412 ,  H01L21/823437 ,  H01L29/66621

    摘要： The recess channel transistor includes: a semiconductor substrate including a device insulation layer defining an activation region in which recesses are formed; insulation buffer patterns, each of which is formed at an opening of the recess on a surface of the substrate; gates, each of which includes a recess gate formed in the recess and a top gate formed on the substrate; spacers, each of which is formed at both sides of the gate; and a source region and a drain region formed at both sides of each gate on the surface of the substrate, where the source and drain regions have an even doping profile due to the existence of insulation buffer patterns. Accordingly, characteristics of the transistor can be prevented from deteriorating due to misalignment of the top gate with the recess gate.

    摘要翻译： 所述凹槽通道晶体管包括：半导体衬底，其包括限定形成有凹部的激活区域的器件绝缘层; 绝缘缓冲图案，其各自形成在基板的表面上的凹部的开口处; 栅极，每个栅极包括形成在凹部中的凹槽和形成在衬底上的顶栅; 间隔件，每个间隔件形成在门的两侧; 以及源极区和漏极区，形成在衬底表面上的每个栅极的两侧，其中由于存在绝缘缓冲图案，源区和漏区具有均匀的掺杂分布。 因此，可以防止晶体管的特性由于顶栅与凹槽的不对准而劣化。