公开(公告)号：US08472875B2

公开(公告)日：2013-06-25

申请号：US12510313

申请日：2009-07-28

申请人： Sang Woo Ji ,  Hyeon Soo Kim ,  Jae Hun Jeong

发明人： Sang Woo Ji ,  Hyeon Soo Kim ,  Jae Hun Jeong

IPC分类号： H04B7/00

CPC分类号： G07C5/008 ,  G07C5/085 ,  H04W4/04

摘要： The present invention relates to technology which performs wireless communications of a vehicle by selectively operating a wireless communications module of a vehicle connected to an AP (Access Point) which collects vehicle information according to the state of the vehicle. The present invention includes a vehicle information storage unit that stores vehicle information collected from each electronic control unit of a vehicle; a wireless communications module that performs wireless communications with an AP (Access Point); and a wireless communications controller that controls a connection state of the AP with the wireless communications module by selectively operating the wireless communications module according to the state of the vehicle, and sends the vehicle information to the AP through the wireless communications module.

摘要翻译： 本发明涉及通过选择性地操作与根据车辆的状态收集车辆信息的AP（接入点）连接的车辆的无线通信模块来执行车辆的无线通信的技术。 本发明包括车辆信息存储单元，其存储从车辆的每个电子控制单元收集的车辆信息; 执行与AP（接入点）的无线通信的无线通信模块; 以及无线通信控制器，其通过根据所述车辆的状态选择性地操作所述无线通信模块来控制所述AP与所述无线通信模块的连接状态，并且通过所述无线通信模块将所述车辆信息发送到所述AP。

公开(公告)号：US20100075608A1

公开(公告)日：2010-03-25

申请号：US12510313

申请日：2009-07-28

申请人： Sang Woo Ji ,  Hyeon Soo Kim ,  Jae Hun Jeong

发明人： Sang Woo Ji ,  Hyeon Soo Kim ,  Jae Hun Jeong

IPC分类号： H04B7/00

CPC分类号： G07C5/008 ,  G07C5/085 ,  H04W4/04

摘要： The present invention relates to technology which performs wireless communications of a vehicle by selectively operating a wireless communications module of a vehicle connected to an AP (Access Point) which collects vehicle information according to the state of the vehicle. The present invention includes a vehicle information storage unit that stores vehicle information collected from each electronic control unit of a vehicle; a wireless communications module that performs wireless communications with an AP (Access Point); and a wireless communications controller that controls a connection state of the AP with the wireless communications module by selectively operating the wireless communications module according to the state of the vehicle, and sends the vehicle information to the AP through the wireless communications module.

摘要翻译： 本发明涉及通过选择性地操作与根据车辆的状态收集车辆信息的AP（接入点）连接的车辆的无线通信模块来执行车辆的无线通信的技术。 本发明包括车辆信息存储单元，其存储从车辆的每个电子控制单元收集的车辆信息; 执行与AP（接入点）的无线通信的无线通信模块; 以及无线通信控制器，其通过根据所述车辆的状态选择性地操作所述无线通信模块来控制所述AP与所述无线通信模块的连接状态，并且通过所述无线通信模块将所述车辆信息发送到所述AP。

公开(公告)号：US08691703B2

公开(公告)日：2014-04-08

申请号：US13585166

申请日：2012-08-14

申请人： Suk Ki Kim ,  Hyeon Soo Kim

发明人： Suk Ki Kim ,  Hyeon Soo Kim

IPC分类号： H01L21/302

CPC分类号： H01L21/76801 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11524

摘要： A semiconductor device is manufactured by, inter alia: forming second gate lines, arranged at wider intervals than each of first gate lines and first gate lines, over a semiconductor substrate; forming a multi-layered insulating layer over the entire surface of the semiconductor substrate including the first and the second gate lines; etching the multi-layered insulating layer so that a part of the multi-layered insulating layer remains between the first gate lines and the first and the second gate lines; forming mask patterns formed on the respective remaining multi-layered insulating layers and each formed to cover the multi-layered insulating layer between the second gate lines; and etching the multi-layered insulating layers remaining between the first gate lines and between the first and the second gate lines and not covered by the mask patterns so that the first and the second gate lines are exposed.

摘要翻译： 特别是通过在半导体衬底上形成比第一栅极线和第一栅极线的间隔更宽的第二栅极线制造半导体器件; 在包括第一和第二栅极线的半导体衬底的整个表面上形成多层绝缘层; 蚀刻多层绝缘层，使得多层绝缘层的一部分保留在第一栅极线与第一和第二栅极线之间; 形成在所述剩余的多层绝缘层上形成的掩模图案，并且形成为覆盖所述第二栅极线之间的所述多层绝缘层; 并且蚀刻保留在第一栅极线之间以及第一和第二栅极线之间的多层绝缘层，并且不被掩模图案覆盖，使得第一和第二栅极线暴露。

公开(公告)号：US20120199938A1

公开(公告)日：2012-08-09

申请号：US13108501

申请日：2011-05-16

申请人： Sung Min Hwang ,  Hyeon Soo Kim

发明人： Sung Min Hwang ,  Hyeon Soo Kim

IPC分类号： H01L29/06 ,  H01L21/764

CPC分类号： H01L21/768 ,  H01L21/76224 ,  H01L21/7682 ,  H01L21/76834 ,  H01L27/11524

摘要： A semiconductor memory device includes a semiconductor substrate defining active regions partitioned by an isolation region, conductive lines spaced apart from each other and crossing the active regions over the semiconductor substrate, a thin film pattern formed on a top portion of the conductive lines having opening portions exposing part of the conductive lines in a width wider than a width of the conductive lines, an insulating layer filling the opening portions and formed over the thin film pattern, and an air gap formed between the conductive lines below the insulating layer and the thin film pattern.

摘要翻译： 半导体存储器件包括限定由隔离区分隔的有源区的半导体衬底，彼此间隔开并与半导体衬底上的有源区交叉的导电线，形成在导电线的顶部上的薄膜图案，其具有开口部分 将导电线的一部分暴露于宽于导电线的宽度的宽度，填充开口部分并形成在薄膜图案上的绝缘层，以及形成在绝缘层和薄膜之下的导电线之间的气隙 模式。

公开(公告)号：US6114241A

公开(公告)日：2000-09-05

申请号：US338525

申请日：1999-06-23

申请人： Hyung Bok Choi ,  Chang Seo Park ,  Hyeon Soo Kim

发明人： Hyung Bok Choi ,  Chang Seo Park ,  Hyeon Soo Kim

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76814

摘要： The present invention relates to a method of manufacturing a semiconductor device, which is capable of effectively removing a WO.sub.3 film generated on a tungsten silicide during contact hole etch that opens a gate electrode including the tungsten silicide as its top film by selectively etching a interlayer insulating film. The WO.sub.3 film is removed by a washing process using an alkaline solution such as TMAH(tetra-methyl-ammonium-hydroxide) or NH.sub.4 OH solution. The effective removal of the WO.sub.3 film reduces the contact resistance between a conductive material layer to be formed in he contact hole by a later process and the gate electrode, thereby improving the operative characteristics of the semiconductor device. TMAH solution used in the washing process has a high selectivity of WO.sub.3 film relative to a thermal oxide film or a BPSG film that is generally used as the interlayer insulating film. Thus, the present invention is capable of minimizing the damage of the side parts of the interlayer insulating film during the washing process after contact etching.

摘要翻译： 本发明涉及一种制造半导体器件的方法，该方法能够有效地除去在接触孔蚀刻期间在硅化钨上产生的WO 3膜，其通过选择性地蚀刻层间绝缘体来打开包括硅化钨作为其顶部膜的栅电极 电影。 通过使用碱性溶液如TMAH（四甲基氢氧化铵）或NH 4 OH溶液的洗涤方法除去WO 3膜。 WO3膜的有效去除通过后续工艺在接触孔中形成的导电材料层与栅电极之间的接触电阻降低，从而提高半导体器件的操作特性。 在洗涤过程中使用的TMAH溶液相对于通常用作层间绝缘膜的热氧化膜或BPSG膜具有高选择性的WO 3膜。 因此，本发明能够最小化接触蚀刻后的洗涤工序中的层间绝缘膜的侧面部分的损伤。

公开(公告)号：US08674425B2

公开(公告)日：2014-03-18

申请号：US13108501

申请日：2011-05-16

申请人： Sung Min Hwang ,  Hyeon Soo Kim

发明人： Sung Min Hwang ,  Hyeon Soo Kim

IPC分类号： H01L29/76

CPC分类号： H01L21/768 ,  H01L21/76224 ,  H01L21/7682 ,  H01L21/76834 ,  H01L27/11524

摘要： A semiconductor memory device includes a semiconductor substrate defining active regions partitioned by an isolation region, conductive lines spaced apart from each other and crossing the active regions over the semiconductor substrate, a thin film pattern formed on a top portion of the conductive lines having opening portions exposing part of the conductive lines in a width wider than a width of the conductive lines, an insulating layer filling the opening portions and formed over the thin film pattern, and an air gap formed between the conductive lines below the insulating layer and the thin film pattern.

摘要翻译： 半导体存储器件包括限定由隔离区分隔的有源区的半导体衬底，彼此间隔开并与半导体衬底上的有源区交叉的导电线，形成在导电线的顶部上的薄膜图案，其具有开口部分 将导电线的一部分暴露于宽于导电线的宽度的宽度，填充开口部分并形成在薄膜图案上的绝缘层，以及形成在绝缘层和薄膜之下的导电线之间的气隙 模式。

公开(公告)号：US20110159681A1

公开(公告)日：2011-06-30

申请号：US12973278

申请日：2010-12-20

申请人： Sung Min Hwang ,  Hyeon Soo Kim

发明人： Sung Min Hwang ,  Hyeon Soo Kim

IPC分类号： H01L21/28

CPC分类号： H01L21/76224 ,  H01L21/3081 ,  H01L27/11521 ,  H01L29/40114

摘要： A method of manufacturing a nonvolatile memory device includes forming a tunnel insulating layer over a semiconductor substrate, forming tunnel insulating patterns to expose portions of the semiconductor substrate by removing portions of the tunnel insulating layer formed over isolation regions of the semiconductor substrate, forming a first conductive layer of single crystalline material over the tunnel insulating patterns and exposed portions of the semiconductor substrate, and forming a second conductive layer over the first conductive layer.

摘要翻译： 一种制造非易失性存储器件的方法包括在半导体衬底上形成隧道绝缘层，形成隧道绝缘图案以通过去除在半导体衬底的隔离区上形成的隧道绝缘层的部分来暴露半导体衬底的部分，形成第一 隧道绝缘图案和半导体衬底的暴露部分上的单晶材料的导电层，并在第一导电层上形成第二导电层。

公开(公告)号：US06551913B1

公开(公告)日：2003-04-22

申请号：US09343480

申请日：1999-06-30

申请人： Hyeon Soo Kim ,  Chang Seo Park

发明人： Hyeon Soo Kim ,  Chang Seo Park

IPC分类号： H01L213205

CPC分类号： H01L29/665

摘要： The present invention relates to a semiconductor technology and more specifically to a method of fabricating a gate electrode of a semiconductor device, where a re-oxidation process that may cause an abnormal oxidation can be eliminated. In a polysilicon/silicide structure or polysilicon/metal structure of gate electrode, a step of etching side parts of gate electrode is performed without any etch mask after gate patterning. Here, the etch can be made by wet or dry etch using an etchant having high selectivity of polysilicon film to a gate oxide film, so that the damaged gate oxide part during the gate patterning is allowed not to make a role of the gate insulating film itself, thereby eliminating the re-oxidation process.

摘要翻译： 本发明涉及一种半导体技术，更具体地涉及制造可能引起异常氧化的再氧化工艺的半导体器件的栅电极的制造方法。 在栅极电极的多晶硅/硅化物结构或多晶硅/金属结构中，在栅极图案化之后，没有任何蚀刻掩模执行刻蚀栅极的侧面部分的步骤。 这里，可以通过使用具有多晶硅膜对栅极氧化膜的高选择性的蚀刻剂的湿蚀刻或干法蚀刻来进行蚀刻，使得栅极图案化期间损坏的栅极氧化物部分不被起到栅极绝缘膜的作用 本身，从而消除再氧化过程。

公开(公告)号：US06503806B1

公开(公告)日：2003-01-07

申请号：US09472202

申请日：1999-12-27

申请人： Hyeon Soo Kim

发明人： Hyeon Soo Kim

IPC分类号： H01L21336

CPC分类号： H01L29/6656 ,  H01L21/28061 ,  H01L21/28247

摘要： Disclosed is a method for forming a gate electrode of a semiconductor device, the method comprises the steps of: stacking a gate oxide film, a doped first silicon film, a diffusion preventing film, a metal film having a high melting point and a mask insulating film on a semiconductor substrate; forming a gate electrode by patterning a resultant stack structure; forming a second silicon film on an entire surface of a resultant structure; forming an oxidation preventing film on an entire surface of a resultant structure; forming a spacer on a side wall of the gate electrode by anisotrophically etching the oxidation preventing film and the second silicon film; and forming a gate reoxide film on the semiconductor substrate by oxidizing the semiconductor substrate.

摘要翻译： 公开了一种形成半导体器件的栅电极的方法，该方法包括以下步骤：堆叠栅极氧化膜，掺杂第一硅膜，扩散防止膜，具有高熔点的金属膜和掩模绝缘 半导体衬底上的膜; 通过图案化所得的堆叠结构形成栅电极; 在所得结构的整个表面上形成第二硅膜; 在所得结构的整个表面上形成氧化防止膜; 通过各向异性蚀刻氧化防止膜和第二硅膜，在栅电极的侧壁上形成间隔物; 以及通过氧化半导体衬底在半导体衬底上形成栅极氧化膜。

公开(公告)号：US6165884A

公开(公告)日：2000-12-26

申请号：US457162

申请日：1999-12-08

申请人： Sang Moo Lee ,  Hyeon Soo Kim ,  In Seok Yeo

发明人： Sang Moo Lee ,  Hyeon Soo Kim ,  In Seok Yeo

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L21/3205

CPC分类号： H01L21/28052

摘要： A method of forming a gate electrode in a semiconductor device which can easily perform etching process for forming the gate electrode and reduce the resistivity of a gate electrode, is disclosed. In the present invention, a gate oxide layer, an amorphous silicon layer and a tungsten silicide layer are sequentially formed on a semiconductor substrate. A mask oxide pattern is then formed on the tungsten silicide layer in the shape of a gate electrode. Next, the tungsten silicide layer and the amorphous silicon layer are etched using the mask oxide pattern as an etch mask, to form a gate electrode. Thereafter, the amorphous silicon layer and the tungsten silicide layer of the gate electrode are thermal-treated by RTP spike annealing and an oxide layer is then formed on the side wall of the gate electrode. According to the present invention, by reducing resistivity of a tungsten silicide layer, it is possible to apply a conventional gate electrode material to high integration device over 1GDRAM, thereby lowering cost to develop a new gate electrode material. Furthermore, etching process for forming a gate electrode is easily performed when using the tungsten silicide layer as the gate electrode material, thereby obtaining uniform gate electrode. As a result, the reliability of a device is improved.

摘要翻译： 公开了一种在半导体器件中形成栅电极的方法，其可以容易地进行用于形成栅电极的蚀刻工艺并降低栅电极的电阻率。 在本发明中，在半导体衬底上依次形成栅极氧化层，非晶硅层和硅化钨层。 然后在栅电极形状的硅化钨层上形成掩模氧化物图案。 接下来，使用掩模氧化物图案作为蚀刻掩模来蚀刻硅化钨层和非晶硅层，以形成栅电极。 此后，通过RTP尖峰退火对栅电极的非晶硅层和硅化钨层进行热处理，然后在栅电极的侧壁上形成氧化物层。 根据本发明，通过降低硅化钨层的电阻率，可以将传统的栅极电极材料应用于超过1GDRAM的高集成度器件，从而降低开发新的栅电极材料的成本。 此外，当使用硅化钨层作为栅电极材料时，容易进行用于形成栅电极的蚀刻工艺，从而获得均匀的栅电极。 结果，提高了设备​​的可靠性。