公开(公告)号：US07405425B2

公开(公告)日：2008-07-29

申请号：US11232306

申请日：2005-09-20

申请人： Sang-Gab Kim ,  Shi-Yul Kim ,  Hong-Sick Park ,  Hee-Hwan Choe ,  Hong-Kee Chin ,  Min-Seok Oh

发明人： Sang-Gab Kim ,  Shi-Yul Kim ,  Hong-Sick Park ,  Hee-Hwan Choe ,  Hong-Kee Chin ,  Min-Seok Oh

IPC分类号： H01L29/04

CPC分类号： H01L29/66765 ,  G02F1/1368 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458

摘要： A thin film transistor includes a gate electrode on a substrate, a gate insulating layer on the substrate, a channel pattern, a source electrode and a drain electrode. The channel pattern includes a semiconductor pattern formed on the gate electrode and overlaying the gate electrode as well as first and second conductive adhesive patterns formed on the semiconductor pattern and spaced apart from each other. The source electrode includes a first barrier pattern, a source pattern and a first capping pattern sequentially formed on the first conductive adhesive pattern. The drain electrode includes a second barrier pattern, a drain pattern and a second capping pattern sequentially formed on the second conductive adhesive pattern. Etched portions of the first and second conductive adhesive patterns have a substantially vertical profile to prevent the exposure of the source and drain electrodes, thereby improving the characteristics of the thin film transistor.

摘要翻译： 薄膜晶体管包括衬底上的栅电极，衬底上的栅极绝缘层，沟道图案，源电极和漏电极。 沟道图案包括形成在栅电极上并覆盖栅电极的半导体图案以及形成在半导体图案上并彼此间隔开的第一和第二导电粘合剂图案。 源电极包括顺序地形成在第一导电粘合剂图案上的第一阻挡图案，源图案和第一封盖图案。 漏电极包括顺序地形成在第二导电粘合剂图案上的第二阻挡图案，漏极图案和第二封盖图案。 第一和第二导电粘合剂图案的蚀刻部分具有基本垂直的轮廓，以防止源极和漏极的暴露，从而改善薄膜晶体管的特性。

公开(公告)号：US20090017574A1

公开(公告)日：2009-01-15

申请号：US12146763

申请日：2008-06-26

申请人： Sang-Gab Kim ,  Shi-Yul Kim ,  Hong-Sick Park ,  Hee-Hwan Choe ,  Hong-Kee Chin ,  Min-Seok Oh

发明人： Sang-Gab Kim ,  Shi-Yul Kim ,  Hong-Sick Park ,  Hee-Hwan Choe ,  Hong-Kee Chin ,  Min-Seok Oh

IPC分类号： H01L21/336 ,  H01L33/00

CPC分类号： H01L29/66765 ,  G02F1/1368 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458

摘要： A thin film transistor includes a gate electrode on a substrate, a gate insulating layer on the substrate, a channel pattern, a source electrode and a drain electrode. The channel pattern includes a semiconductor pattern formed on the gate electrode and overlaying the gate electrode as well as first and second conductive adhesive patterns formed on the semiconductor pattern and spaced apart from each other. The source electrode includes a first barrier pattern, a source pattern and a first capping pattern sequentially formed on the first conductive adhesive pattern. The drain electrode includes a second barrier pattern, a drain pattern and a second capping pattern sequentially formed on the second conductive adhesive pattern. Etched portions of the first and second conductive adhesive patterns have a substantially vertical profile to prevent the exposure of the source and drain electrodes, thereby improving the characteristics of the thin film transistor.

摘要翻译： 薄膜晶体管包括衬底上的栅电极，衬底上的栅极绝缘层，沟道图案，源电极和漏电极。 沟道图案包括形成在栅电极上并覆盖栅电极的半导体图案以及形成在半导体图案上并彼此间隔开的第一和第二导电粘合剂图案。 源电极包括顺序地形成在第一导电粘合剂图案上的第一阻挡图案，源图案和第一封盖图案。 漏电极包括顺序地形成在第二导电粘合剂图案上的第二阻挡图案，漏极图案和第二封盖图案。 第一和第二导电粘合剂图案的蚀刻部分具有基本垂直的轮廓，以防止源极和漏极的暴露，从而改善薄膜晶体管的特性。

公开(公告)号：US07588972B2

公开(公告)日：2009-09-15

申请号：US12146763

申请日：2008-06-26

申请人： Sang-Gab Kim ,  Shi-Yul Kim ,  Hong-Sick Park ,  Hee-Hwan Choe ,  Hong-Kee Chin ,  Min-Seok Oh

发明人： Sang-Gab Kim ,  Shi-Yul Kim ,  Hong-Sick Park ,  Hee-Hwan Choe ,  Hong-Kee Chin ,  Min-Seok Oh

IPC分类号： H01L21/00

CPC分类号： H01L29/66765 ,  G02F1/1368 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458

摘要： A thin film transistor includes a gate electrode on a substrate, a gate insulating layer on the substrate, a channel pattern, a source electrode and a drain electrode. The channel pattern includes a semiconductor pattern formed on the gate electrode and overlaying the gate electrode as well as first and second conductive adhesive patterns formed on the semiconductor pattern and spaced apart from each other. The source electrode includes a first barrier pattern, a source pattern and a first capping pattern sequentially formed on the first conductive adhesive pattern. The drain electrode includes a second barrier pattern, a drain pattern and a second capping pattern sequentially formed on the second conductive adhesive pattern. Etched portions of the first and second conductive adhesive patterns have a substantially vertical profile to prevent the exposure of the source and drain electrodes, thereby improving the characteristics of the thin film transistor.

摘要翻译： 薄膜晶体管包括衬底上的栅电极，衬底上的栅极绝缘层，沟道图案，源电极和漏电极。 沟道图案包括形成在栅电极上并覆盖栅电极的半导体图案以及形成在半导体图案上并彼此间隔开的第一和第二导电粘合剂图案。 源电极包括顺序地形成在第一导电粘合剂图案上的第一阻挡图案，源图案和第一封盖图案。 漏电极包括顺序地形成在第二导电粘合剂图案上的第二阻挡图案，漏极图案和第二封盖图案。 第一和第二导电粘合剂图案的蚀刻部分具有基本垂直的轮廓，以防止源极和漏极的暴露，从而改善薄膜晶体管的特性。

公开(公告)号：US20060118786A1

公开(公告)日：2006-06-08

申请号：US11232306

申请日：2005-09-20

申请人： Sang-Gab Kim ,  Shi--Yul Kim ,  Hong-Sick Park ,  Hee-Hwan Choe ,  Hong-Kee Chin ,  Min-Seok Oh

发明人： Sang-Gab Kim ,  Shi--Yul Kim ,  Hong-Sick Park ,  Hee-Hwan Choe ,  Hong-Kee Chin ,  Min-Seok Oh

IPC分类号： H01L29/04

CPC分类号： H01L29/66765 ,  G02F1/1368 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458

摘要： A thin film transistor includes a gate electrode on a substrate, a gate insulating layer on the substrate, a channel pattern, a source electrode and a drain electrode. The channel pattern includes a semiconductor pattern formed on the gate electrode and overlaying the gate electrode as well as first and second conductive adhesive patterns formed on the semiconductor pattern and spaced apart from each other. The source electrode includes a first barrier pattern, a source pattern and a first capping pattern sequentially formed on the first conductive adhesive pattern. The drain electrode includes a second barrier pattern, a drain pattern and a second capping pattern sequentially formed on the second conductive adhesive pattern. Etched portions of the first and second conductive adhesive patterns have a substantially vertical profile to prevent the exposure of the source and drain electrodes, thereby improving the characteristics of the thin film transistor.

公开(公告)号：US20060192906A1

公开(公告)日：2006-08-31

申请号：US11356853

申请日：2006-02-17

申请人： Hye-Young Ryu ,  Jang-Soo Kim ,  Sang-Gab Kim ,  Hong-Kee Chin ,  Min-Seok Oh ,  Hee-Hwan Choe ,  Shi-Yul Kim

发明人： Hye-Young Ryu ,  Jang-Soo Kim ,  Sang-Gab Kim ,  Hong-Kee Chin ,  Min-Seok Oh ,  Hee-Hwan Choe ,  Shi-Yul Kim

IPC分类号： G02F1/136

CPC分类号： G02F1/136286 ,  G02F1/133345 ,  G02F1/1362 ,  G02F2001/136222 ,  G02F2202/02

摘要： A thin film transistor array panel is provided, which includes a gate line, a data line intersecting the gate line, a storage electrode apart from the gate and data lines, a thin film transistor connected to the gate and data lines and having a drain electrode, a pixel electrode connected to the drain electrode, a first insulating layer over the thin film transistor and disposed under the pixel electrode, and a second insulating layer disposed on the first insulating layer and having an opening exposing the first insulating layer on the storage electrode.

摘要翻译： 提供薄膜晶体管阵列面板，其包括栅极线，与栅极线相交的数据线，与栅极和数据线分开的存储电极，连接到栅极和数据线并具有漏极的薄膜晶体管 连接到漏电极的像素电极，薄膜晶体管上的第一绝缘层，并且设置在像素电极下方;第二绝缘层，设置在第一绝缘层上，并且具有使存储电极上的第一绝缘层露出的开口 。

公开(公告)号：US20060131581A1

公开(公告)日：2006-06-22

申请号：US11255801

申请日：2005-10-21

申请人： Sang-Gab Kim ,  Min-Seok Oh ,  Hong-Kee Chin ,  Jeong-Min Park ,  Shi-Yul Kim ,  Hee-Hwan Choe

发明人： Sang-Gab Kim ,  Min-Seok Oh ,  Hong-Kee Chin ,  Jeong-Min Park ,  Shi-Yul Kim ,  Hee-Hwan Choe

IPC分类号： H01L29/04

CPC分类号： H01L29/458 ,  G02F2001/136236 ,  H01L27/124 ,  H01L27/1288

摘要： A method for manufacturing a TFT array panel including forming a gate line having a gate electrode on a insulating layer, a gate insulating layer on the gate line, a semiconductor on the gate insulating layer, an ohmic contact on the semiconductor, a data line having a source electrode and a drain electrode apart form the source electrode on the ohmic contact, a passivation layer having a contact hole to expose the drain electrode, and a pixel electrode connected to the drain electrode through the contact hole. The drain electrode and the source electrode are formed by a photolithography using a negative photoresist pattern. The negative photoresist pattern includes a first portion having a first thickness corresponding to a channel area, a second portion having a second thickness corresponding to a data line area, and a third portion having a third thickness corresponding to another area.

摘要翻译： 一种TFT阵列板的制造方法，包括在绝缘层上形成具有栅电极的栅极线，栅极线上的栅极绝缘层，栅极绝缘层上的半导体，半导体上的欧姆接触，数据线， 源电极和漏电极分开形成欧姆接触上的源电极，具有露出漏电极的接触孔的钝化层和通过接触孔连接到漏电极的像素电极。 漏电极和源电极通过使用负光致抗蚀剂图案的光刻形成。 负型光致抗蚀剂图案包括具有对应于沟道区域的第一厚度的第一部分，具有对应于数据线区域的第二厚度的第二部分和具有对应于另一区域的第三厚度的第三部分。

公开(公告)号：US08305507B2

公开(公告)日：2012-11-06

申请号：US11356853

申请日：2006-02-17

申请人： Hye-Young Ryu ,  Jang-Soo Kim ,  Sang-Gab Kim ,  Hong-Kee Chin ,  Min-Seok Oh ,  Hee-Hwan Choe ,  Shi-Yul Kim

发明人： Hye-Young Ryu ,  Jang-Soo Kim ,  Sang-Gab Kim ,  Hong-Kee Chin ,  Min-Seok Oh ,  Hee-Hwan Choe ,  Shi-Yul Kim

IPC分类号： G02F1/1343

CPC分类号： G02F1/136286 ,  G02F1/133345 ,  G02F1/1362 ,  G02F2001/136222 ,  G02F2202/02

摘要： A thin film transistor array panel is provided, which includes a gate line, a data line intersecting the gate line, a storage electrode apart from the gate and data lines, a thin film transistor connected to the gate and data lines and having a drain electrode, a pixel electrode connected to the drain electrode, a first insulating layer over the thin film transistor and disposed under the pixel electrode, and a second insulating layer disposed on the first insulating layer and having an opening exposing the first insulating layer on the storage electrode.

摘要翻译： 提供薄膜晶体管阵列面板，其包括栅极线，与栅极线相交的数据线，与栅极和数据线分开的存储电极，连接到栅极和数据线并具有漏极的薄膜晶体管 连接到漏电极的像素电极，薄膜晶体管上的第一绝缘层，并且设置在像素电极下方;第二绝缘层，设置在第一绝缘层上，并且具有使存储电极上的第一绝缘层露出的开口 。

公开(公告)号：US07688417B2

公开(公告)日：2010-03-30

申请号：US11255801

申请日：2005-10-21

申请人： Sang-Gab Kim ,  Min-Seok Oh ,  Hong-Kee Chin ,  Jeong-Min Park ,  Shi-Yul Kim ,  Hee-Hwan Choe

发明人： Sang-Gab Kim ,  Min-Seok Oh ,  Hong-Kee Chin ,  Jeong-Min Park ,  Shi-Yul Kim ,  Hee-Hwan Choe

IPC分类号： G02F1/1333 ,  G02F1/133 ,  G02F1/13

CPC分类号： H01L29/458 ,  G02F2001/136236 ,  H01L27/124 ,  H01L27/1288

摘要： A method for manufacturing a TFT array panel including forming a gate line having a gate electrode on a insulating layer, a gate insulating layer on the gate line, a semiconductor on the gate insulating layer, an ohmic contact on the semiconductor, a data line having a source electrode and a drain electrode apart form the source electrode on the ohmic contact, a passivation layer having a contact hole to expose the drain electrode, and a pixel electrode connected to the drain electrode through the contact hole. The drain electrode and the source electrode are formed by a photolithography using a negative photoresist pattern. The negative photoresist pattern includes a first portion having a first thickness corresponding to a channel area, a second portion having a second thickness corresponding to a data line area, and a third portion having a third thickness corresponding to another area.

摘要翻译： 一种TFT阵列板的制造方法，包括在绝缘层上形成具有栅电极的栅极线，栅极线上的栅极绝缘层，栅极绝缘层上的半导体，半导体上的欧姆接触，数据线， 源电极和漏电极分开形成欧姆接触上的源电极，具有露出漏电极的接触孔的钝化层和通过接触孔连接到漏电极的像素电极。 漏电极和源电极通过使用负光致抗蚀剂图案的光刻形成。 负型光致抗蚀剂图案包括具有对应于沟道区域的第一厚度的第一部分，具有对应于数据线区域的第二厚度的第二部分和具有对应于另一区域的第三厚度的第三部分。

公开(公告)号：US20100140626A1

公开(公告)日：2010-06-10

申请号：US12704503

申请日：2010-02-11

申请人： Sang-Gab Kim ,  Min-Seok Oh ,  Hong-Kee Chin ,  Jeong-Min Park ,  Shi-Yul Kim ,  Hee-Hwan Choe

发明人： Sang-Gab Kim ,  Min-Seok Oh ,  Hong-Kee Chin ,  Jeong-Min Park ,  Shi-Yul Kim ,  Hee-Hwan Choe

IPC分类号： H01L27/12

CPC分类号： H01L29/458 ,  G02F2001/136236 ,  H01L27/124 ,  H01L27/1288

摘要： A method for manufacturing a TFT array panel including forming a gate line having a gate electrode on a insulating layer, a gate insulating layer on the gate line, a semiconductor on the gate insulating layer, an ohmic contact on the semiconductor, a data line having a source electrode and a drain electrode apart form the source electrode on the ohmic contact, a passivation layer having a contact hole to expose the drain electrode, and a pixel electrode connected to the drain electrode through the contact hole. The drain electrode and the source electrode are formed by a photolithography using a negative photoresist pattern. The negative photoresist pattern includes a first portion having a first thickness corresponding to a channel area, a second portion having a second thickness corresponding to a data line area, and a third portion having a third thickness corresponding to another area.

摘要翻译： 一种TFT阵列板的制造方法，包括在绝缘层上形成具有栅电极的栅极线，栅极线上的栅极绝缘层，栅极绝缘层上的半导体，半导体上的欧姆接触，数据线， 源电极和漏电极分开形成欧姆接触上的源电极，具有露出漏电极的接触孔的钝化层和通过接触孔连接到漏电极的像素电极。 漏电极和源电极通过使用负光致抗蚀剂图案的光刻形成。 负型光致抗蚀剂图案包括具有对应于沟道区域的第一厚度的第一部分，具有对应于数据线区域的第二厚度的第二部分和具有对应于另一区域的第三厚度的第三部分。

公开(公告)号：US07876412B2

公开(公告)日：2011-01-25

申请号：US12704503

申请日：2010-02-11

申请人： Sang-Gab Kim ,  Min-Seok Oh ,  Hong-Kee Chin ,  Jeong-Min Park ,  Shi-Yul Kim ,  Hee-Hwan Choe

发明人： Sang-Gab Kim ,  Min-Seok Oh ,  Hong-Kee Chin ,  Jeong-Min Park ,  Shi-Yul Kim ,  Hee-Hwan Choe

IPC分类号： G02F1/1343 ,  G02F1/1337

CPC分类号： H01L29/458 ,  G02F2001/136236 ,  H01L27/124 ,  H01L27/1288

摘要： A method for manufacturing a TFT array panel including forming a gate line having a gate electrode on a insulating layer, a gate insulating layer on the gate line, a semiconductor on the gate insulating layer, an ohmic contact on the semiconductor, a data line having a source electrode and a drain electrode apart form the source electrode on the ohmic contact, a passivation layer having a contact hole to expose the drain electrode, and a pixel electrode connected to the drain electrode through the contact hole. The drain electrode and the source electrode are formed by a photolithography using a negative photoresist pattern. The negative photoresist pattern includes a first portion having a first thickness corresponding to a channel area, a second portion having a second thickness corresponding to a data line area, and a third portion having a third thickness corresponding to another area.

摘要翻译： 一种TFT阵列板的制造方法，包括在绝缘层上形成具有栅电极的栅极线，栅极线上的栅极绝缘层，栅极绝缘层上的半导体，半导体上的欧姆接触，数据线， 源电极和漏电极分开形成欧姆接触上的源电极，具有露出漏电极的接触孔的钝化层和通过接触孔连接到漏电极的像素电极。 漏电极和源电极通过使用负光致抗蚀剂图案的光刻形成。 负型光致抗蚀剂图案包括具有对应于沟道区域的第一厚度的第一部分，具有对应于数据线区域的第二厚度的第二部分和具有对应于另一区域的第三厚度的第三部分。