公开(公告)号：US20090017574A1

公开(公告)日：2009-01-15

申请号：US12146763

申请日：2008-06-26

申请人： Sang-Gab Kim ,  Shi-Yul Kim ,  Hong-Sick Park ,  Hee-Hwan Choe ,  Hong-Kee Chin ,  Min-Seok Oh

发明人： Sang-Gab Kim ,  Shi-Yul Kim ,  Hong-Sick Park ,  Hee-Hwan Choe ,  Hong-Kee Chin ,  Min-Seok Oh

IPC分类号： H01L21/336 ,  H01L33/00

CPC分类号： H01L29/66765 ,  G02F1/1368 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458

摘要： A thin film transistor includes a gate electrode on a substrate, a gate insulating layer on the substrate, a channel pattern, a source electrode and a drain electrode. The channel pattern includes a semiconductor pattern formed on the gate electrode and overlaying the gate electrode as well as first and second conductive adhesive patterns formed on the semiconductor pattern and spaced apart from each other. The source electrode includes a first barrier pattern, a source pattern and a first capping pattern sequentially formed on the first conductive adhesive pattern. The drain electrode includes a second barrier pattern, a drain pattern and a second capping pattern sequentially formed on the second conductive adhesive pattern. Etched portions of the first and second conductive adhesive patterns have a substantially vertical profile to prevent the exposure of the source and drain electrodes, thereby improving the characteristics of the thin film transistor.

摘要翻译： 薄膜晶体管包括衬底上的栅电极，衬底上的栅极绝缘层，沟道图案，源电极和漏电极。 沟道图案包括形成在栅电极上并覆盖栅电极的半导体图案以及形成在半导体图案上并彼此间隔开的第一和第二导电粘合剂图案。 源电极包括顺序地形成在第一导电粘合剂图案上的第一阻挡图案，源图案和第一封盖图案。 漏电极包括顺序地形成在第二导电粘合剂图案上的第二阻挡图案，漏极图案和第二封盖图案。 第一和第二导电粘合剂图案的蚀刻部分具有基本垂直的轮廓，以防止源极和漏极的暴露，从而改善薄膜晶体管的特性。

公开(公告)号：US07588972B2

公开(公告)日：2009-09-15

申请号：US12146763

申请日：2008-06-26

申请人： Sang-Gab Kim ,  Shi-Yul Kim ,  Hong-Sick Park ,  Hee-Hwan Choe ,  Hong-Kee Chin ,  Min-Seok Oh

发明人： Sang-Gab Kim ,  Shi-Yul Kim ,  Hong-Sick Park ,  Hee-Hwan Choe ,  Hong-Kee Chin ,  Min-Seok Oh

IPC分类号： H01L21/00

CPC分类号： H01L29/66765 ,  G02F1/1368 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458

摘要： A thin film transistor includes a gate electrode on a substrate, a gate insulating layer on the substrate, a channel pattern, a source electrode and a drain electrode. The channel pattern includes a semiconductor pattern formed on the gate electrode and overlaying the gate electrode as well as first and second conductive adhesive patterns formed on the semiconductor pattern and spaced apart from each other. The source electrode includes a first barrier pattern, a source pattern and a first capping pattern sequentially formed on the first conductive adhesive pattern. The drain electrode includes a second barrier pattern, a drain pattern and a second capping pattern sequentially formed on the second conductive adhesive pattern. Etched portions of the first and second conductive adhesive patterns have a substantially vertical profile to prevent the exposure of the source and drain electrodes, thereby improving the characteristics of the thin film transistor.

摘要翻译： 薄膜晶体管包括衬底上的栅电极，衬底上的栅极绝缘层，沟道图案，源电极和漏电极。 沟道图案包括形成在栅电极上并覆盖栅电极的半导体图案以及形成在半导体图案上并彼此间隔开的第一和第二导电粘合剂图案。 源电极包括顺序地形成在第一导电粘合剂图案上的第一阻挡图案，源图案和第一封盖图案。 漏电极包括顺序地形成在第二导电粘合剂图案上的第二阻挡图案，漏极图案和第二封盖图案。 第一和第二导电粘合剂图案的蚀刻部分具有基本垂直的轮廓，以防止源极和漏极的暴露，从而改善薄膜晶体管的特性。

公开(公告)号：US20060118786A1

公开(公告)日：2006-06-08

申请号：US11232306

申请日：2005-09-20

申请人： Sang-Gab Kim ,  Shi--Yul Kim ,  Hong-Sick Park ,  Hee-Hwan Choe ,  Hong-Kee Chin ,  Min-Seok Oh

发明人： Sang-Gab Kim ,  Shi--Yul Kim ,  Hong-Sick Park ,  Hee-Hwan Choe ,  Hong-Kee Chin ,  Min-Seok Oh

IPC分类号： H01L29/04

CPC分类号： H01L29/66765 ,  G02F1/1368 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458

摘要： A thin film transistor includes a gate electrode on a substrate, a gate insulating layer on the substrate, a channel pattern, a source electrode and a drain electrode. The channel pattern includes a semiconductor pattern formed on the gate electrode and overlaying the gate electrode as well as first and second conductive adhesive patterns formed on the semiconductor pattern and spaced apart from each other. The source electrode includes a first barrier pattern, a source pattern and a first capping pattern sequentially formed on the first conductive adhesive pattern. The drain electrode includes a second barrier pattern, a drain pattern and a second capping pattern sequentially formed on the second conductive adhesive pattern. Etched portions of the first and second conductive adhesive patterns have a substantially vertical profile to prevent the exposure of the source and drain electrodes, thereby improving the characteristics of the thin film transistor.

公开(公告)号：US07405425B2

公开(公告)日：2008-07-29

申请号：US11232306

申请日：2005-09-20

申请人： Sang-Gab Kim ,  Shi-Yul Kim ,  Hong-Sick Park ,  Hee-Hwan Choe ,  Hong-Kee Chin ,  Min-Seok Oh

发明人： Sang-Gab Kim ,  Shi-Yul Kim ,  Hong-Sick Park ,  Hee-Hwan Choe ,  Hong-Kee Chin ,  Min-Seok Oh

IPC分类号： H01L29/04

CPC分类号： H01L29/66765 ,  G02F1/1368 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458

摘要： A thin film transistor includes a gate electrode on a substrate, a gate insulating layer on the substrate, a channel pattern, a source electrode and a drain electrode. The channel pattern includes a semiconductor pattern formed on the gate electrode and overlaying the gate electrode as well as first and second conductive adhesive patterns formed on the semiconductor pattern and spaced apart from each other. The source electrode includes a first barrier pattern, a source pattern and a first capping pattern sequentially formed on the first conductive adhesive pattern. The drain electrode includes a second barrier pattern, a drain pattern and a second capping pattern sequentially formed on the second conductive adhesive pattern. Etched portions of the first and second conductive adhesive patterns have a substantially vertical profile to prevent the exposure of the source and drain electrodes, thereby improving the characteristics of the thin film transistor.

摘要翻译： 薄膜晶体管包括衬底上的栅电极，衬底上的栅极绝缘层，沟道图案，源电极和漏电极。 沟道图案包括形成在栅电极上并覆盖栅电极的半导体图案以及形成在半导体图案上并彼此间隔开的第一和第二导电粘合剂图案。 源电极包括顺序地形成在第一导电粘合剂图案上的第一阻挡图案，源图案和第一封盖图案。 漏电极包括顺序地形成在第二导电粘合剂图案上的第二阻挡图案，漏极图案和第二封盖图案。 第一和第二导电粘合剂图案的蚀刻部分具有基本垂直的轮廓，以防止源极和漏极的暴露，从而改善薄膜晶体管的特性。

公开(公告)号：US20070111412A1

公开(公告)日：2007-05-17

申请号：US11600481

申请日：2006-11-15

申请人： Min-Seok Oh ,  Jeong-Min Park ,  Sang-Gab Kim ,  Hong-Kee Chin ,  Chang-Oh Jeong ,  Hong-Sick Park ,  Shi-Yul Kim

发明人： Min-Seok Oh ,  Jeong-Min Park ,  Sang-Gab Kim ,  Hong-Kee Chin ,  Chang-Oh Jeong ,  Hong-Sick Park ,  Shi-Yul Kim

IPC分类号： H01L21/84

CPC分类号： H01L21/32139 ,  H01L21/0273 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288

摘要： In one embodiment, a thin film transistor array display panel and method of manufacturing the same are provided. A method includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact layer on the gate line; forming a data layer on the ohmic contact layer; forming a photosensitive pattern on the data layer; etching the data layer to form a data line including a source electrode and a drain electrode that is opposite to the source electrode; reflowing the photosensitive pattern to cover side surfaces of the source electrode and the drain electrode; and etching the ohmic contact layer using the reflowed photosensitive pattern as a mask.

摘要翻译： 在一个实施例中，提供了薄膜晶体管阵列显示面板及其制造方法。 一种方法包括在基板上形成栅极线; 在栅极线上形成栅极绝缘层，半导体层和欧姆接触层; 在欧姆接触层上形成数据层; 在数据层上形成感光图案; 蚀刻数据层以形成包括与源电极相对的源电极和漏电极的数据线; 回流感光图案以覆盖源电极和漏电极的侧表面; 并使用回流感光图案作为掩模蚀刻欧姆接触层。

公开(公告)号：US20090184319A1

公开(公告)日：2009-07-23

申请号：US12328487

申请日：2008-12-04

申请人： Sang-Gab Kim ,  Min-Seok Oh ,  Yu-Gwang Jeong ,  Hong-Sick Park ,  Shi-Yul Kim ,  Jang-Soo Kim ,  Shin-Il Choi

发明人： Sang-Gab Kim ,  Min-Seok Oh ,  Yu-Gwang Jeong ,  Hong-Sick Park ,  Shi-Yul Kim ,  Jang-Soo Kim ,  Shin-Il Choi

IPC分类号： H01L29/04 ,  H01L21/336

CPC分类号： G02F1/136286 ,  G02F2001/136295 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/458

摘要： A method of manufacturing a display substrate is described. In the method, a gate line and a gate electrode are formed on a base substrate. A source metal layer is formed on the base substrate having the gate line and the gate electrode. A data line, a source electrode and a drain electrode are formed by etching the source metal layer by using an etching gas. An additive gas is provided to the base substrate having the drain electrode so that the additive gas reacts with an etching component of the etching gas to remove a by-product formed at an exposed portion of the data line, the source electrode and drain electrode. Thus, corrosion of the fine pattern due to an etching gas may be prevented and/or reduced.

摘要翻译： 对制造显示基板的方法进行说明。 在该方法中，在基底基板上形成栅极线和栅电极。 在具有栅极线和栅电极的基底基板上形成源极金属层。 通过使用蚀刻气体蚀刻源极金属层来形成数据线，源电极和漏电极。 向具有漏电极的基底基板提供添加气体，使得添加气体与蚀刻气体的蚀刻部件反应，以除去在数据线，源电极和漏电极的暴露部分形成的副产物。 因此，可以防止和/或减少由蚀刻气体引起的精细图案的腐蚀。

公开(公告)号：US07638800B2

公开(公告)日：2009-12-29

申请号：US10501597

申请日：2002-07-29

申请人： Seung-Hee Yu ,  Mun-Pyo Hong ,  Soo-Guy Rho ,  Nam-Seok Rho ,  Keun-Kyu Song ,  Hee-Hwan Choe ,  Bo-Sung Kim ,  Sang-Gab Kim ,  Sung-Chul Kang ,  Hong-Sick Park

发明人： Seung-Hee Yu ,  Mun-Pyo Hong ,  Soo-Guy Rho ,  Nam-Seok Rho ,  Keun-Kyu Song ,  Hee-Hwan Choe ,  Bo-Sung Kim ,  Sang-Gab Kim ,  Sung-Chul Kang ,  Hong-Sick Park

IPC分类号： H01L21/84

CPC分类号： G02F1/136286 ,  G02F2001/136295

摘要： First, a Cr film and a CrOx film are deposited and patterned using an etchant including 8-12% Ce(NH4)2(NO3)6, 10-20% NH3 and remaining ultra pure water to form a gate wire including a plurality of gate lines, a plurality of gate electrodes and a plurality of gate pads. Next, a gate insulating film, a semiconductor layer and an ohmic contact layer are formed in sequence. A Cr film and CrOx film are deposited in sequence and patterned using an etchant including 8-12% Ce(NH4)2(NO3)6, 10-20% NH3 and remaining ultra pure water to form a data wire including a plurality of data lines, a plurality of source electrodes, a plurality of drain electrodes and a plurality of data pads. A passivation layer is deposited and patterned to form a plurality of contact holes respectively exposing the drain electrodes, the gate pads and the data pads. A transparent conductive material or a reflective conductive material is deposited and patterned to form a plurality of pixel electrodes, a plurality of subsidiary gate pads and a plurality of subsidiary data pads electrically connected to the drain electrodes, the gate pads and the data pads, respectively. The gate lines and the data lines with low reflectance are used as a light-blocking film for blocking the light leakage between the pixel areas, and do not increase the black brightness. Accordingly, a separate black matrix need not be provided on the color filter panel, thereby securing both aperture ratio of the pixel and high contrast ratio.

摘要翻译： 首先，使用包括8-12％Ce（NH 4）2（NO 3）6，10-20％NH 3和剩余的超纯水的蚀刻剂沉积和图案化Cr膜和CrOx膜，以形成包括多个 栅极线，多个栅电极和多个栅极焊盘。 接下来，依次形成栅极绝缘膜，半导体层和欧姆接触层。 依次沉积Cr膜和CrOx膜，并使用包括8-12％Ce（NH 4）2（NO 3）6，10-20％NH 3和剩余的超纯水的蚀刻剂进行图案化以形成包括多个数据的数据线 线，多个源电极，多个漏电极和多个数据焊盘。 钝化层被沉积并图案化以形成分别暴露漏电极，栅极焊盘和数据焊盘的多个接触孔。 沉积透明导电材料或反射导电材料以形成多个像素电极，分别与漏电极，栅极焊盘和数据焊盘电连接的多个辅助栅极焊盘和多个辅助数据焊盘 。 栅极线和低反射率的数据线被用作阻挡像素区域之间的漏光的遮光膜，并且不增加黑色亮度。 因此，不需要在滤色器面板上设置单独的黑矩阵，从而确保像素的开口率和高对比度。

公开(公告)号：US20050173732A1

公开(公告)日：2005-08-11

申请号：US10501597

申请日：2002-07-29

申请人： Seung-Hee Yu ,  Mun-Pyo Hong ,  Soo-Guy Rho ,  Nam-Seok Rho ,  Keun-Kyu Song ,  Hee-Hwan Choe ,  Bo-Sung Kim ,  Sang-Gab Kim ,  Sung-Chul Kang ,  Hong-Sick Park

发明人： Seung-Hee Yu ,  Mun-Pyo Hong ,  Soo-Guy Rho ,  Nam-Seok Rho ,  Keun-Kyu Song ,  Hee-Hwan Choe ,  Bo-Sung Kim ,  Sang-Gab Kim ,  Sung-Chul Kang ,  Hong-Sick Park

IPC分类号： G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/30 ,  H01L21/28 ,  H01L21/3205 ,  H01L23/52 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L27/10

CPC分类号： G02F1/136286 ,  G02F2001/136295

摘要： First, a Cr film and a CrOx film are deposited and patterned using an etchant including 8-12% Ce(NH4)2(NO3)6, 10-20% NH3 and remaining ultra pure water to form a gate wire including a plurality of gate lines, a plurality of gate electrodes and a plurality of gate pads. Next, a gate insulating film, a semiconductor layer and an ohmic contact layer are formed in sequence. A Cr film and CrOx film are deposited in sequence and patterned using an etchant including 8-12% Ce(N114)2(NO3)6, 10-20% NH3 and remaining ultra pure water to form a data wire including a plurality of data lines, a plurality of source electrodes, a plurality of drain electrodes and a plurality of data pads. A passivation layer is deposited and pattered to form a plurality of contact holes respectively exposing the drain electrodes, the gate pads and the data pads. A transparent conductive material or a reflective conductive material is deposited and patterned to form a plurality of pixel electrodes, a plurality of subsidiary gate pads and a plurality of subsidiary data pads electrically connected to the drain electrodes, the gate pads and the data pads, respectively. The gate lines and the data lines with low reflectance are used as a light-blocking film for blocking the light leakage between the pixel areas, and do not increase the black brightness. Accordingly, a separate black matrix need not be provided on the color filter panel, thereby securing both aperture ration of the pixel and high contrast ratio.

摘要翻译： 首先，使用包括8-12％Ce（NH 4）2（NO 3）6的蚀刻剂沉积和图案化Cr膜和CrOx膜， SUB，10-20％NH 3和剩余的超纯水，以形成包括多个栅极线，多个栅电极和多个栅极焊盘的栅极线。 接下来，依次形成栅极绝缘膜，半导体层和欧姆接触层。 依次沉积Cr膜和CrOx膜，并使用包括8-12％Ce（N11 4）2（NO 3）3的蚀刻剂进行图案化， ）6N，10-20％NH 3和剩余的超纯水，以形成数据线，其包括多条数据线，多个源电极，多个漏极 电极和多个数据焊盘。 钝化层被沉积并图案化以形成分别暴露漏电极，栅极焊盘和数据焊盘的多个接触孔。 沉积透明导电材料或反射导电材料以形成多个像素电极，分别与漏电极，栅极焊盘和数据焊盘电连接的多个辅助栅极焊盘和多个辅助数据焊盘 。 栅极线和低反射率的数据线被用作阻挡像素区域之间的漏光的遮光膜，并且不增加黑色亮度。 因此，不需要在滤色器面板上设置单独的黑矩阵，从而确保像素的孔径比和高对比度。

公开(公告)号：US08058114B2

公开(公告)日：2011-11-15

申请号：US12797527

申请日：2010-06-09

申请人： Jang-Soo Kim ,  Hong-Long Ning ,  Bong-Kyun Kim ,  Hong-Sick Park ,  Shi-Yul Kim ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Yang-Ho Bae ,  Pil-Sang Yun ,  Jong-Hyun Choung ,  Sun-Young Hong ,  Ki-Won Kim ,  Byeong-Jin Lee ,  Young-Wook Lee ,  Jong-In Kim ,  Byeong-Beom Kim ,  Nam-Seok Suh

发明人： Jang-Soo Kim ,  Hong-Long Ning ,  Bong-Kyun Kim ,  Hong-Sick Park ,  Shi-Yul Kim ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Yang-Ho Bae ,  Pil-Sang Yun ,  Jong-Hyun Choung ,  Sun-Young Hong ,  Ki-Won Kim ,  Byeong-Jin Lee ,  Young-Wook Lee ,  Jong-In Kim ,  Byeong-Beom Kim ,  Nam-Seok Suh

IPC分类号： H01L21/84 ,  H01L21/336

CPC分类号： G02F1/13458 ,  G02F1/136286 ,  G02F2001/136295 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1288

摘要： A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.

摘要翻译： 栅极线包括形成在基底基板上的第一籽晶层和形成在第一籽晶层上的第一金属层。 在基底基板上形成第一绝缘层。 在基底基板上形成第二绝缘层。 这里，在与栅极线交叉的方向上通过第二绝缘层形成线沟槽。 数据线包括形成在线沟槽下方的第二晶种层和形成在线沟槽中的第二金属层。 像素电极形成在基底基板的像素区域中。 因此，使用绝缘层形成预定深度的沟槽，并且通过电镀方法形成金属层，从而可以形成具有足够厚度的金属线。

公开(公告)号：US20100261322A1

公开(公告)日：2010-10-14

申请号：US12797527

申请日：2010-06-09

申请人： Jang-Soo Kim ,  Hong-Long Ning ,  Bong-Kyun Kim ,  Hong-Sick Park ,  Shi-Yul Kim ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Yang-Ho Bae ,  Pil-Sang Yun ,  Jong-Hyun Choung ,  Sun-Young Hong ,  Ki-Won Kim ,  Byeong-Jin Lee ,  Young-Wook Lee ,  Jong-In Kim ,  Byeong-Beom Kim ,  Nam-Seok Suh

发明人： Jang-Soo Kim ,  Hong-Long Ning ,  Bong-Kyun Kim ,  Hong-Sick Park ,  Shi-Yul Kim ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Yang-Ho Bae ,  Pil-Sang Yun ,  Jong-Hyun Choung ,  Sun-Young Hong ,  Ki-Won Kim ,  Byeong-Jin Lee ,  Young-Wook Lee ,  Jong-In Kim ,  Byeong-Beom Kim ,  Nam-Seok Suh

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： G02F1/13458 ,  G02F1/136286 ,  G02F2001/136295 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1288

摘要： A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.

摘要翻译： 栅极线包括形成在基底基板上的第一籽晶层和形成在第一籽晶层上的第一金属层。 在基底基板上形成第一绝缘层。 在基底基板上形成第二绝缘层。 这里，在与栅极线交叉的方向上通过第二绝缘层形成线沟槽。 数据线包括形成在线沟槽下方的第二晶种层和形成在线沟槽中的第二金属层。 像素电极形成在基底基板的像素区域中。 因此，使用绝缘层形成预定深度的沟槽，并且通过电镀方法形成金属层，从而可以形成具有足够厚度的金属线。