公开(公告)号：US09786387B2

公开(公告)日：2017-10-10

申请号：US14729295

申请日：2015-06-03

申请人： Sang-Uhn Cha ,  Hoi-Ju Chung ,  Jong-Pil Son ,  Kwang-Il Park ,  Seong-Jin Jang

发明人： Sang-Uhn Cha ,  Hoi-Ju Chung ,  Jong-Pil Son ,  Kwang-Il Park ,  Seong-Jin Jang

IPC分类号： G06F11/10 ,  G11C29/00 ,  G11C29/52 ,  G11C11/15 ,  G11C29/04 ,  G11C29/44

CPC分类号： G11C29/52 ,  G06F11/1048 ,  G11C11/15 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C29/702 ,  G11C2029/0411 ,  G11C2029/4402

摘要： A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array.