利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

128 条记录 (耗时 0.031 秒)

    Anti-fuse, anti-fuse circuit including the same, and method of fabricating the anti-fuse
    2.
    发明授权
    Anti-fuse, anti-fuse circuit including the same, and method of fabricating the anti-fuse 有权
    防熔丝，反熔丝电路包括相同，以及制造防熔丝的方法

    公开(公告)号：US08514648B2

    公开(公告)日：2013-08-20

    申请号：US13051998

    申请日：2011-03-18

    申请人： Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

    发明人： Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

    IPC分类号： G11C17/18

    CPC分类号： H01L23/5252 ,  G11C17/16 ,  G11C29/785 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided are an anti-fuse, an anti-fuse circuit, and a method of fabricating the anti-fuse. The anti-fuse includes a semiconductor substrate, an isolation region, a channel diffusion region, a gate oxide layer, and a gate electrode. The semiconductor substrate includes a top surface and a bottom portion, the bottom portion of the semiconductor substrate having a first conductivity type. The isolation region is disposed inward from the top surface of the semiconductor substrate to a first depth. The channel diffusion region is disposed inward from the top surface of the semiconductor substrate to a second depth, the second depth located at a depth where the channel diffusion region meets an upper boundary of the bottom portion of the semiconductor substrate. The channel diffusion region is surrounded by the isolation region, the first depth is a greater distance from the top surface of the semiconductor substrate than the second depth, and the channel diffusion region has a second conductivity type opposite to the first conductivity type. The gate oxide layer is disposed on the channel diffusion region, and the gate electrode is disposed on the gate oxide layer to cover a top surface of the gate oxide layer.

    摘要翻译： 提供反熔丝，反熔丝电路和制造反熔丝的方法。 反熔丝包括半导体衬底，隔离区，沟道扩散区，栅极氧化层和栅电极。 半导体衬底包括顶表面和底部，半导体衬底的底部具有第一导电类型。 隔离区域从半导体衬底的顶表面向内设置到第一深度。 沟道扩散区域从半导体衬底的顶表面向内设置到第二深度，第二深度位于沟道扩散区域与半导体衬底的底部的上边界相交的深度处。 沟道扩散区域由隔离区域包围，第一深度比半导体衬底的顶表面的距离大于第二深度，并且沟道扩散区域具有与第一导电类型相反的第二导电类型。 栅极氧化层设置在沟道扩散区上，并且栅电极设置在栅极氧化层上以覆盖栅极氧化物层的顶表面。

    ANTI-FUSE, ANTI-FUSE CIRCUIT INCLUDING THE SAME, AND METHOD OF FABRICATING THE ANTI-FUSE
    3.
    发明申请
    ANTI-FUSE, ANTI-FUSE CIRCUIT INCLUDING THE SAME, AND METHOD OF FABRICATING THE ANTI-FUSE 有权
    抗保险丝，包括其中的防熔丝电路以及制造防熔丝的方法

    公开(公告)号：US20110267915A1

    公开(公告)日：2011-11-03

    申请号：US13051998

    申请日：2011-03-18

    申请人： Jong-Pil SON ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

    发明人： Jong-Pil SON ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

    IPC分类号： G11C8/10 ,  H01L29/78 ,  H01L27/088

    CPC分类号： H01L23/5252 ,  G11C17/16 ,  G11C29/785 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided are an anti-fuse, an anti-fuse circuit, and a method of fabricating the anti-fuse. The anti-fuse includes a semiconductor substrate, an isolation region, a channel diffusion region, a gate oxide layer, and a gate electrode. The semiconductor substrate includes a top surface and a bottom portion, the bottom portion of the semiconductor substrate having a first conductivity type. The isolation region is disposed inward from the top surface of the semiconductor substrate to a first depth. The channel diffusion region is disposed inward from the top surface of the semiconductor substrate to a second depth, the second depth located at a depth where the channel diffusion region meets an upper boundary of the bottom portion of the semiconductor substrate. The channel diffusion region is surrounded by the isolation region, the first depth is a greater distance from the top surface of the semiconductor substrate than the second depth, and the channel diffusion region has a second conductivity type opposite to the first conductivity type. The gate oxide layer is disposed on the channel diffusion region, and the gate electrode is disposed on the gate oxide layer to cover a top surface of the gate oxide layer.

    摘要翻译： 提供反熔丝，反熔丝电路和制造反熔丝的方法。 反熔丝包括半导体衬底，隔离区，沟道扩散区，栅极氧化层和栅电极。 半导体衬底包括顶表面和底部，半导体衬底的底部具有第一导电类型。 隔离区域从半导体衬底的顶表面向内设置到第一深度。 沟道扩散区域从半导体衬底的顶表面向内设置到第二深度，第二深度位于沟道扩散区域与半导体衬底的底部的上边界相交的深度处。 沟道扩散区域由隔离区域包围，第一深度比半导体衬底的顶表面的距离大于第二深度，并且沟道扩散区域具有与第一导电类型相反的第二导电类型。 栅极氧化层设置在沟道扩散区上，并且栅电极设置在栅极氧化层上以覆盖栅极氧化物层的顶表面。

    Fuse circuit and semiconductor memory device including the same
    4.
    发明授权
    Fuse circuit and semiconductor memory device including the same 有权
    保险丝电路和包括其的半导体存储器件

    公开(公告)号：US08599635B2

    公开(公告)日：2013-12-03

    申请号：US13205966

    申请日：2011-08-09

    申请人： Jin-Ho Kim ,  Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Seung-Hoon Oh ,  Ju-Seop Park

    发明人： Jin-Ho Kim ,  Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Seung-Hoon Oh ,  Ju-Seop Park

    IPC分类号： G11C17/18

    CPC分类号： G11C29/027 ,  G11C17/16 ,  G11C29/04

    摘要： A fuse circuit includes a program unit, a sensing unit and a control unit. The program unit is programmed in response to a program signal, and outputs a program output signal in response to a sensing enable signal. The sensing unit includes a variable resistor unit that has a resistance that varies based on a control signal, and generates a sensing output signal based on the resistance of the variable resistor unit and the program output signal. The control unit generates the control signal having a value changed depending on operation modes, and performs a verification operation with respect to the program unit based on the sensing output signal to generate a verification result. The program unit may be re-programmed based on the verification result.

    摘要翻译： 熔丝电路包括程序单元，感测单元和控制单元。 程序单元响应于程序信号被编程，并且响应于感测使能信号而输出程序输出信号。 感测单元包括具有基于控制信号而变化的电阻的可变电阻器单元，并且基于可变电阻器单元的电阻和程序输出信号产生感测输出信号。 控制单元产生具有根据操作模式改变的值的控制信号，并且基于感测输出信号执行关于节目单元的验证操作以产生验证结果。 程序单元可以基于验证结果重新编程。

    Circuit and method for sampling valid command using extended valid address window in double pumped address scheme memory device
    9.
    发明授权
    Circuit and method for sampling valid command using extended valid address window in double pumped address scheme memory device 有权
    在双泵浦地址方案存储器件中使用扩展有效地址窗口采样有效命令的电路和方法

    公开(公告)号：US07656742B2

    公开(公告)日：2010-02-02

    申请号：US12128464

    申请日：2008-05-28

    申请人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Jeong-Don Lim ,  Kwang-Il Park ,  Ho-Young Song ,  Woo-Jin Lee

    发明人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Jeong-Don Lim ,  Kwang-Il Park ,  Ho-Young Song ,  Woo-Jin Lee

    IPC分类号： G11C8/00

    CPC分类号： G06F12/02 ,  G11C7/1078 ,  G11C7/109

    摘要： Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.

    摘要翻译： 提供了一种用于在双抽取地址方案存储器件中使用扩展用于高速操作的有效地址窗口来对有效命令进行采样的电路和方法。 扩展有效地址窗口的方法包括：在时钟信号的第一周期输入有效的命令信号和第一地址信号; 在时钟信号的第二周期输入第二地址信号; 响应于命令信号和地址信号分别产生解码的命令信号和扩展的第一和第二内部地址信号; 以及响应于解码的命令信号来锁存和解码扩展的第一和第二内部地址信号。

    Semiconductor devices, a system including semiconductor devices and methods thereof
    10.
    发明申请
    Semiconductor devices, a system including semiconductor devices and methods thereof 有权
    半导体器件，包括半导体器件的系统及其方法

    公开(公告)号：US20090267813A1

    公开(公告)日：2009-10-29

    申请号：US12453109

    申请日：2009-04-29

    申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

    发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

    IPC分类号： H03M7/00

    CPC分类号： H03K19/00346 ,  H04L25/03866 ,  H04L25/14 ,  H04L25/4908

    摘要： Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

    摘要翻译： 提供半导体器件，包括所述半导体器件的系统及其方法。 半导体器件的示例可以接收被调度用于发送的数据，对接收到的数据内的比特顺序进行加扰，按照给定的伪随机序列排列的加扰顺序。 所接收的数据可以是平衡的，使得等于第一逻辑电平的接收数据内的第一比特数与等于第二逻辑电平的接收数据中的第二比特数之间的差异低于阈值。 然后可以发送平衡和加扰的接收数据。 示例半导体器件可以以任何顺序执行加扰和平衡操作。 类似地，在接收端，另一个半导体器件可以通过对发送的数据进行解扰和不平衡来解码原始数据。 可以基于发送的数据被加扰和平衡的顺序以顺序执行解扰和不平衡操作。