公开(公告)号：US09786387B2

公开(公告)日：2017-10-10

申请号：US14729295

申请日：2015-06-03

申请人： Sang-Uhn Cha ,  Hoi-Ju Chung ,  Jong-Pil Son ,  Kwang-Il Park ,  Seong-Jin Jang

发明人： Sang-Uhn Cha ,  Hoi-Ju Chung ,  Jong-Pil Son ,  Kwang-Il Park ,  Seong-Jin Jang

IPC分类号： G06F11/10 ,  G11C29/00 ,  G11C29/52 ,  G11C11/15 ,  G11C29/04 ,  G11C29/44

CPC分类号： G11C29/52 ,  G06F11/1048 ,  G11C11/15 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C29/702 ,  G11C2029/0411 ,  G11C2029/4402

摘要： A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array.

公开(公告)号：US07814359B2

公开(公告)日：2010-10-12

申请号：US11612800

申请日：2006-12-19

申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-Il Park ,  Sang-Woong Shin ,  Ho-Young Song

发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-Il Park ,  Sang-Woong Shin ,  Ho-Young Song

IPC分类号： G06F12/00

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

摘要： A high-speed double or quadrature data rate interface semiconductor device and a method thereof are provided. A transmitter (e.g., a data transmitting semiconductor device) for high-speed data transmission transmits a first strobe signal and a second strobe signal, which have a phase difference of 90 degrees there-between, a first group (byte of) data, and a second group (byte of) data. The transmitter adjusts the phase of at least one of the first and second strobe signals based on phase-error information fed back from a receiver and then transmits the phase-adjusted strobe signal to the receiver. The receiver receives the first and second strobe signals from the transmitter and receives the first group (byte of) data and the second group (byte of) data using the first and second strobe signals. The receiver does not require a phase-locked loop (PLL) or a delay-locked loop (DLL), thereby decreasing the circuit area and power consumption of the receiver. In addition, since source synchronization is realized using a strobe signal, phase noise can be efficiently removed.

摘要翻译： 提供了一种高速双倍或正交数据速率接口半导体器件及其方法。 用于高速数据传输的发射机（例如，数据传输半导体器件）发射第一选通信号和第二选通信号，第一选通信号和第二选通信号之间具有90度的相位差，第一组（字节）数据和 第二组（字节）数据。 发射机基于从接收机反馈的相位误差信息来调节第一和第二选通信号中的至少一个的相位，然后将相位调整的选通信号发送到接收机。 接收机从发送器接收第一和第二选通信号，并使用第一和第二选通信号接收数据的第一组（字节）和第二组（字节）数据。 接收机不需要锁相环（PLL）或延迟锁定环（DLL），从而减少接收机的电路面积和功耗。 此外，由于使用选通信号实现源同步，因此可以有效地去除相位噪声。

公开(公告)号：US20090225622A1

公开(公告)日：2009-09-10

申请号：US12430163

申请日：2009-04-27

申请人： Seung-Jun Bae ,  Kwang-Il Park ,  Seong-Jin Jang

发明人： Seung-Jun Bae ,  Kwang-Il Park ,  Seong-Jin Jang

IPC分类号： G11C8/00

CPC分类号： G11C7/22 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222

摘要： A circuit for eliminating a skew between data and a clock signal in an interface between a semiconductor memory device and a memory controller includes an edge information storage unit which stores edge information output from the semiconductor memory device, a pseudo data pattern generating unit which outputs pseudo data including a pattern similar to actually transmitted data, a phase detecting unit which receives the edge information from the edge information storage unit and the pseudo data from the pseudo data pattern generating unit to detect a phase difference between the data and the clock signal and generate a corresponding detection result, and a phase control unit which controls a phase of the clock signal according to the corresponding detection result from the phase detecting unit, so as to eliminate a per-data input/output pin skew in a data write and read operation of the semiconductor memory device.

摘要翻译： 一种用于消除半导体存储器件和存储器控制器之间的接口中的数据与时钟信号之间的偏斜的电路，包括存储从半导体存储器件输出的边沿信息的边缘信息存储单元，伪数据模式生成单元，其输出伪 数据，包括与实际发送的数据类似的模式;相位检测单元，其从边缘信息存储单元接收边缘信息，并从伪数据模式产生单元接收伪数据，以检测数据和时钟信号之间的相位差，并产生 相应的检测结果，以及相位控制单元，其根据来自相位检测单元的相应检测结果控制时钟信号的相位，以便消除数据写入和读取操作中的每数据输入/输出引脚偏移 的半导体存储器件。

公开(公告)号：US07768298B2

公开(公告)日：2010-08-03

申请号：US12219213

申请日：2008-07-17

申请人： Kwang-Il Park ,  Seung-Jun Bae ,  Seong-Jin Jang

发明人： Kwang-Il Park ,  Seung-Jun Bae ,  Seong-Jin Jang

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/017545

摘要： A system including a plurality of transmission lines, a transmitter outputting respective signals to each of the plurality of transmission lines, a receiver receiving each of the plurality of signals via respective transmission lines, the receiver including a connection path connected to a termination voltage, a plurality of termination circuits distributed along the connection path, each termination circuit receiving a unique termination voltage from the connection path, receiving a respective signal and outputting a terminated input signal, a reference voltage generator including multiple reference voltage generator units connected to a common voltage, each reference voltage generator unit uniquely receiving at least one unique termination voltage and outputting a reference voltage, and a plurality of data input buffers receiving respective signals and an appropriate reference voltage of the multiple reference voltages output from the reference voltage generator.

摘要翻译： 一种包括多个传输线的系统，向多个传输线中的每一个输出相应信号的发射机，经由各个传输线接收多个信号中的每一个的接收机，所述接收机包括连接到终端电压的连接路径， 多个终端电路沿着连接路径分布，每个终端电路从连接路径接收唯一的终端电压，接收相应信号并输出​​终止的输入信号;参考电压发生器，包括连接到公共电压的多个参考电压发生器单元， 每个参考电压发生器单元独特地接收至少一个唯一的终端电压并输出参考电压，以及多个数据输入缓冲器，其接收相应的信号和从参考电压发生器输出的多个参考电压的适当参考电压。

公开(公告)号：US20100091600A1

公开(公告)日：2010-04-15

申请号：US12635785

申请日：2009-12-11

申请人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Jeong-Don Lim ,  Kwang-Il Park ,  Ho-Young Song ,  Woo-Jin Lee

发明人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Jeong-Don Lim ,  Kwang-Il Park ,  Ho-Young Song ,  Woo-Jin Lee

IPC分类号： G11C8/00 ,  G11C8/18

CPC分类号： G06F12/02 ,  G11C7/1078 ,  G11C7/109

摘要： Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.

摘要翻译： 提供了一种用于在双抽取地址方案存储器件中使用扩展用于高速操作的有效地址窗口来对有效命令进行采样的电路和方法。 扩展有效地址窗口的方法包括：在时钟信号的第一周期输入有效的命令信号和第一地址信号; 在时钟信号的第二周期输入第二地址信号; 响应于命令信号和地址信号分别产生解码的命令信号和扩展的第一和第二内部地址信号; 以及响应于解码的命令信号来锁存和解码扩展的第一和第二内部地址信号。

公开(公告)号：US07403040B2

公开(公告)日：2008-07-22

申请号：US11790014

申请日：2007-04-23

申请人： Kwang-Il Park ,  Seung-Jun Bae ,  Seong-Jin Jang

发明人： Kwang-Il Park ,  Seung-Jun Bae ,  Seong-Jin Jang

IPC分类号： H03K19/094 ,  H03K19/0175

CPC分类号： H03K19/017545

摘要： A system including a plurality of transmission lines, a transmitter outputting respective signals to each of the plurality of transmission lines, a receiver receiving each of the plurality of signals via respective transmission lines, the receiver including a connection path connected to a termination voltage, a plurality of termination circuits distributed along the connection path, each termination circuit receiving a unique termination voltage from the connection path, receiving a respective signal and outputting a terminated input signal, a reference voltage generator including multiple reference voltage generator units connected to a common voltage, each reference voltage generator unit uniquely receiving at least one unique termination voltage and outputting a reference voltage, and a plurality of data input buffers receiving respective signals and an appropriate reference voltage of the multiple reference voltages output from the reference voltage generator.

摘要翻译： 一种包括多个传输线的系统，向多个传输线中的每一个输出相应信号的发射机，经由各个传输线接收多个信号中的每一个的接收机，所述接收机包括连接到终端电压的连接路径， 多个终端电路沿着连接路径分布，每个终端电路从连接路径接收唯一的终端电压，接收相应的信号并输出​​终止的输入信号;参考电压发生器，包括连接到公共电压的多个参考电压发生器单元， 每个参考电压发生器单元独特地接收至少一个唯一的终端电压并输出参考电压，以及多个数据输入缓冲器，其接收相应的信号和从参考电压发生器输出的多个参考电压的适当参考电压。

公开(公告)号：US20060062286A1

公开(公告)日：2006-03-23

申请号：US11128795

申请日：2005-05-13

申请人： Kwang-Il Park ,  Seong-Jin Jang ,  Ho-Young Song

发明人： Kwang-Il Park ,  Seong-Jin Jang ,  Ho-Young Song

IPC分类号： H04B1/38

CPC分类号： G11C7/1072 ,  G11C29/50 ,  G11C29/50012 ,  G11C2207/2254

摘要： For data training in a memory device, a selecting unit selects a subset of data bit patterns received from a controlling device. In addition, a storing unit comprised of memory cells of the memory device stores the selected subset of data bit patterns. Such stored data bit patterns are then sent back to the controlling device that determines the level of data skew. Such data training more accurately reflects the actual paths and environments of the transmitted data bits.

摘要翻译： 对于存储器件中的数据训练，选择单元选择从控制装置接收的数据位模式的子集。 此外，由存储器件的存储器单元组成的存储单元存储所选择的数据位模式子集。 然后将这种存储的数据位模式发送回确定数据偏移水平的控制设备。 这种数据训练更准确地反映了传输数据位的实际路径和环境。

公开(公告)号：US08541893B2

公开(公告)日：2013-09-24

申请号：US11229257

申请日：2005-09-16

申请人： Sung-Hoon Kim ,  Young-Chul Cho ,  Kwang-Il Park ,  Seong-Jin Jang

发明人： Sung-Hoon Kim ,  Young-Chul Cho ,  Kwang-Il Park ,  Seong-Jin Jang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device and a power line arrangement method are disclosed. The semiconductor memory device includes a plurality of pads, each pad including an upper pad and a lower pad arranged below the upper pad, wherein pad power lines are arranged below the lower pads of the plurality of pads in a direction of crossing the pads to interconnect the pads that transmit the same level of electrical power among the plurality of pads.

摘要翻译： 公开了半导体存储器件和电源线布置方法。 所述半导体存储器件包括多个焊盘，每个焊盘包括布置在所述上​​焊盘下方的上焊盘和下焊盘，其中焊盘电源线布置在所述多个焊盘的下焊盘的下方，该焊盘跨越所述焊盘以互连 所述焊盘在所述多个焊盘之间传输相同水平的电力。

公开(公告)号：US08045663B2

公开(公告)日：2011-10-25

申请号：US12029518

申请日：2008-02-12

申请人： Seung-Jun Bae ,  Kwang-Il Park ,  Seong-jin Jang

发明人： Seung-Jun Bae ,  Kwang-Il Park ,  Seong-jin Jang

IPC分类号： H04L7/00

CPC分类号： G11C7/22 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222

摘要： A data transmission/reception system can lessen a skew between data and clock signal by substantially reducing a data reception error. The data transmission/reception system using a first clock signal and a second clock signal having a phase difference corresponding to a half of data bit period as compared with the first clock signal includes a skew information extracting unit and a timing control unit. The skew information extracting unit obtains and outputs skew edge information data necessary for a skew removal by sampling data transmitted in a training operating mode as one of the first and second clock signals in a receiving side. The timing control unit receives the skew edge information data through a transmitting side, and compares its phase with a phase of the transmitted data and controls a timing between transmission data and a transmission sampling clock signal applied to a transmission output unit according to the phase comparison result. Time taken in a training operation can be relatively shortened, and circuits of the receiving side can be simplified and power consumption can be relatively reduced.

摘要翻译： 数据发送/接收系统可以通过大幅减少数据接收错误来减少数据和时钟信号之间的偏差。 使用第一时钟信号的数据发送/接收系统和与第一时钟信号相比具有对应于数据位周期的一半的相位差的第二时钟信号包括偏斜信息提取单元和定时控制单元。 偏斜信息提取单元通过在接收侧中作为第一和第二时钟信号之一的训练操作模式中发送的数据采样数据获得并输出偏斜去除所需的倾斜边缘信息数据。 定时控制单元通过发送侧接收偏斜边信息数据，并将其相位与发送数据的相位进行比较，并根据相位比较控制发送数据与发送输出单元的发送采样时钟信号之间的定时 结果。 可以相对缩短训练中所花费的时间，并且可以简化接收侧的电路，并且能够相对减少功耗。

公开(公告)号：US08004911B2

公开(公告)日：2011-08-23

申请号：US12662720

申请日：2010-04-29

申请人： Kwang-Il Park ,  Seong-Jin Jang ,  Ho-Young Song

发明人： Kwang-Il Park ,  Seong-Jin Jang ,  Ho-Young Song

IPC分类号： G11C7/00

CPC分类号： G11C7/1051 ,  G11C7/1066 ,  G11C2207/2254

摘要： An output data strobe signal generating method and a memory system that includes a plurality of semiconductor memory devices, and a memory controller for controlling the semiconductor memory devices, wherein the memory controller provides a command signal and a chip selecting signal to the semiconductor memory devices. One or more of the semiconductor memory devices may detect a read command and a dummy read command in response to the command signal and the chip selecting signal and generate one or more preamble signals based on a calculated preamble cycle number.

摘要翻译： 输出数据选通信号产生方法和包括多个半导体存储器件的存储器系统以及用于控制半导体存储器件的存储器控​​制器，其中存储器控制器向半导体存储器件提供命令信号和片选信号。 一个或多个半导体存储器件可以响应于命令信号和芯片选择信号来检测读取命令和伪读取命令，并且基于所计算的前导码周期数生成一个或多个前导信号。