公开(公告)号：US08735902B2

公开(公告)日：2014-05-27

申请号：US12776965

申请日：2010-05-10

申请人： Sanh D. Tang ,  John Zahurak ,  Siddartha Kondoju ,  Haitao Liu ,  Nishant Sinha

发明人： Sanh D. Tang ,  John Zahurak ,  Siddartha Kondoju ,  Haitao Liu ,  Nishant Sinha

IPC分类号： H01L21/8239

CPC分类号： H01L27/11293 ,  H01L21/823885 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11206 ,  H01L27/11517 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11563 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： Memories and their formation are disclosed. One such memory has a first array of first memory cells extending in a first direction from a first surface of a semiconductor. A second array of second memory cells extends in a second direction, opposite to the first direction, from a second surface of the semiconductor. Both arrays may be non-volatile memory arrays. For example, one of the memory arrays may be a NAND flash memory array, while the other may be a one-time-programmable memory array.

摘要翻译： 记忆及其形成被披露。 一个这样的存储器具有从半导体的第一表面沿第一方向延伸的第一存储单元阵列。 第二阵列的第二存储单元从与半导体的第二表面在第二方向相反的第二方向延伸。 两个阵列可以是非易失性存储器阵列。 例如，存储器阵列之一可以是NAND快闪存储器阵列，而另一个可以是一次可编程存储器阵列。

公开(公告)号：US20110272754A1

公开(公告)日：2011-11-10

申请号：US12776965

申请日：2010-05-10

申请人： Sanh D. Tang ,  John Zahurak ,  Siddartha Kondoju ,  Haitao Liu ,  Nishant Sinha

发明人： Sanh D. Tang ,  John Zahurak ,  Siddartha Kondoju ,  Haitao Liu ,  Nishant Sinha

IPC分类号： H01L29/788 ,  H01L21/336 ,  H01L21/8229 ,  H01L21/76

CPC分类号： H01L27/11293 ,  H01L21/823885 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11206 ,  H01L27/11517 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11563 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： Memories and their formation are disclosed. One such memory has a first array of first memory cells extending in a first direction from a first surface of a semiconductor. A second array of second memory cells extends in a second direction, opposite to the first direction, from a second surface of the semiconductor. Both arrays may be non-volatile memory arrays. For example, one of the memory arrays may be a NAND flash memory array, while the other may be a one-time-programmable memory array.

摘要翻译： 记忆及其形成被披露。 一个这样的存储器具有从半导体的第一表面沿第一方向延伸的第一存储单元阵列。 第二阵列的第二存储单元从与半导体的第二表面在第二方向相反的第二方向延伸。 两个阵列可以是非易失性存储器阵列。 例如，存储器阵列之一可以是NAND快闪存储器阵列，而另一个可以是一次可编程存储器阵列。

公开(公告)号：US20110149656A1

公开(公告)日：2011-06-23

申请号：US12646847

申请日：2009-12-23

申请人： Sanh D. Tang ,  Nishant Sinha ,  John Zahurak

发明人： Sanh D. Tang ,  Nishant Sinha ,  John Zahurak

IPC分类号： G11C16/04 ,  H01L29/788 ,  H01L21/84 ,  H01L21/336

CPC分类号： H01L27/11551 ,  G11C16/0458 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7881

摘要： Embodiments of the invention pertain to vertical memory structures. Embodiments of the invention describe memory nodes comprising two memory cells on opposing sides of a vertical channel separating a source region and a drain region. Embodiments of the invention may utilize floating gate NAND memory cells, polysilicon diodes, MiM diodes, or MiiM diodes. Embodiments of the invention may be used to form flash memory, RRAM, Memristor RAM, Oxide Ram or OTPROM.

摘要翻译： 本发明的实施例涉及垂直存储器结构。 本发明的实施例描述了在分离源区和漏区的垂直沟道的相对侧上包括两个存储单元的存储器节点。 本发明的实施例可以利用浮动栅极NAND存储器单元，多晶硅二极管，MiM二极管或者MiiM二极管。 本发明的实施例可用于形成闪速存储器，RRAM，忆阻器RAM，氧化物Ram或OTPROM。

公开(公告)号：US08508997B2

公开(公告)日：2013-08-13

申请号：US12646847

申请日：2009-12-23

申请人： Sanh D. Tang ,  Nishant Sinha ,  John Zahurak

发明人： Sanh D. Tang ,  Nishant Sinha ,  John Zahurak

IPC分类号： G11C11/34

CPC分类号： H01L27/11551 ,  G11C16/0458 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7881

摘要： Embodiments of the invention pertain to vertical memory structures. Embodiments of the invention describe memory nodes comprising two memory cells on opposing sides of a vertical channel separating a source region and a drain region. Embodiments of the invention may utilize floating gate NAND memory cells, polysilicon diodes, MiM diodes, or MiiM diodes. Embodiments of the invention may be used to form flash memory, RRAM, Memristor RAM, Oxide Ram or OTPROM.

摘要翻译： 本发明的实施例涉及垂直存储器结构。 本发明的实施例描述了在分离源区和漏区的垂直沟道的相对侧上包括两个存储单元的存储器节点。 本发明的实施例可以利用浮动栅极NAND存储器单元，多晶硅二极管，MiM二极管或者MiiM二极管。 本发明的实施例可用于形成闪速存储器，RRAM，忆阻器RAM，氧化物Ram或OTPROM。

公开(公告)号：US20120153357A1

公开(公告)日：2012-06-21

申请号：US12969975

申请日：2010-12-16

申请人： Sanh D. Tang ,  John Zahurak ,  Shane Trapp ,  Krishna K. Parat

发明人： Sanh D. Tang ,  John Zahurak ,  Shane Trapp ,  Krishna K. Parat

IPC分类号： H01L23/538 ,  H01L21/82

CPC分类号： H01L21/8221 ,  H01L27/0688

摘要： Briefly, in accordance with one or more embodiments, multilayer memory device, comprising a lower deck and an upper deck disposed on the lower deck, the decks comprising one or more memory cells coupled via one or more contacts. An isolation layer is disposed between the upper deck, and one or more contacts are formed between the upper deck and the lower deck to couple one or more of the contact lines of the upper deck with one or more contact lines of the lower deck.

摘要翻译： 简而言之，根据一个或多个实施例，多层存储器设备包括设置在下层甲板上的下甲板和上甲板，甲板包括通过一个或多个触点耦合的一个或多个存储单元。 隔离层设置在上甲板之间，并且在上甲板和下甲板之间形成一个或多个触点，以将上甲板中的一个或多个接触线与下甲板的一个或多个接触线接合。

公开(公告)号：US08624300B2

公开(公告)日：2014-01-07

申请号：US12969975

申请日：2010-12-16

申请人： Sanh D. Tang ,  John Zahurak ,  Shane Trapp ,  Krishna K. Parat

发明人： Sanh D. Tang ,  John Zahurak ,  Shane Trapp ,  Krishna K. Parat

IPC分类号： H01L23/52

CPC分类号： H01L21/8221 ,  H01L27/0688

摘要： Briefly, in accordance with one or more embodiments, multilayer memory device, comprising a lower deck and an upper deck disposed on the lower deck, the decks comprising one or more memory cells coupled via one or more contacts. An isolation layer is disposed between the upper deck, and one or more contacts are formed between the upper deck and the lower deck to couple one or more of the contact lines of the upper deck with one or more contact lines of the lower deck.

摘要翻译： 简而言之，根据一个或多个实施例，多层存储器设备包括设置在下层甲板上的下甲板和上甲板，甲板包括通过一个或多个触点耦合的一个或多个存储单元。 隔离层设置在上甲板之间，并且在上甲板和下甲板之间形成一个或多个触点，以将上甲板中的一个或多个接触线与下甲板的一个或多个接触线接合。

公开(公告)号：US20120193703A1

公开(公告)日：2012-08-02

申请号：US13437406

申请日：2012-04-02

申请人： John Zahurak ,  Sanh D. Tang ,  Gurtej S. Sandhu

发明人： John Zahurak ,  Sanh D. Tang ,  Gurtej S. Sandhu

IPC分类号： H01L29/78

CPC分类号： H01L21/823487 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/105 ,  H01L27/24 ,  H01L29/66666 ,  H01L29/7827

摘要： Methods of forming an array of memory cells and memory cells that have pillars. Individual pillars can have a semiconductor post formed of a bulk semiconductor material and a sacrificial cap on the semiconductor post. Source regions can be between columns of the pillars, and gate lines extend along a column of pillars and are spaced apart from corresponding source regions. Each gate line surrounds a portion of the semiconductor posts along a column of pillars. The sacrificial cap structure can be selectively removed to thereby form self-aligned openings that expose a top portion of corresponding semiconductor posts. Individual drain contacts formed in the self-aligned openings are electrically connected to corresponding semiconductor posts.

摘要翻译： 形成具有支柱的存储器单元阵列和存储单元阵列的方法。 单个柱可以具有由半导体柱上的体半导体材料和牺牲帽形成的半导体柱。 源区可以在柱的列之间，并且栅极线沿着柱柱延伸并且与相应的源极区域间隔开。 每个栅极线沿着一列柱围绕半导体柱的一部分。 可以选择性地去除牺牲帽结构，从而形成露出相应半导体柱的顶部的自对准开口。 形成在自对准开口中的单独的漏极触点电连接到相应的半导体柱。

公开(公告)号：US08148222B2

公开(公告)日：2012-04-03

申请号：US12635005

申请日：2009-12-10

申请人： John Zahurak ,  Sanh D. Tang ,  Gurtej S. Sandhu

发明人： John Zahurak ,  Sanh D. Tang ,  Gurtej S. Sandhu

IPC分类号： H01L21/8238

CPC分类号： H01L21/823487 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/105 ,  H01L27/24 ,  H01L29/66666 ,  H01L29/7827

摘要： Methods of forming an array of memory cells and memory cells that have pillars. Individual pillars can have a semiconductor post formed of a bulk semiconductor material and a sacrificial cap on the semiconductor post. Source regions can be between columns of the pillars, and gate lines extend along a column of pillars and are spaced apart from corresponding source regions. Each gate line surrounds a portion of the semiconductor posts along a column of pillars. The sacrificial cap structure can be selectively removed to thereby form self-aligned openings that expose a top portion of corresponding semiconductor posts. Individual drain contacts formed in the self-aligned openings are electrically connected to corresponding semiconductor posts.

摘要翻译： 形成具有支柱的存储器单元阵列和存储单元阵列的方法。 单个柱可以具有由半导体柱上的体半导体材料和牺牲帽形成的半导体柱。 源区可以在柱的列之间，并且栅极线沿着柱柱延伸并且与相应的源极区域间隔开。 每个栅极线沿着一列柱围绕半导体柱的一部分。 可以选择性地去除牺牲帽结构，从而形成露出相应半导体柱的顶部的自对准开口。 形成在自对准开口中的单独的漏极触点电连接到相应的半导体柱。

公开(公告)号：US08362546B2

公开(公告)日：2013-01-29

申请号：US13437406

申请日：2012-04-02

申请人： John Zahurak ,  Sanh D. Tang ,  Gurtej S. Sandhu

发明人： John Zahurak ,  Sanh D. Tang ,  Gurtej S. Sandhu

IPC分类号： H01L29/66

CPC分类号： H01L21/823487 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/105 ,  H01L27/24 ,  H01L29/66666 ,  H01L29/7827

摘要： Methods of forming an array of memory cells and memory cells that have pillars. Individual pillars can have a semiconductor post formed of a bulk semiconductor material and a sacrificial cap on the semiconductor post. Source regions can be between columns of the pillars, and gate lines extend along a column of pillars and are spaced apart from corresponding source regions. Each gate line surrounds a portion of the semiconductor posts along a column of pillars. The sacrificial cap structure can be selectively removed to thereby form self-aligned openings that expose a top portion of corresponding semiconductor posts. Individual drain contacts formed in the self-aligned openings are electrically connected to corresponding semiconductor posts.

公开(公告)号：US20110140195A1

公开(公告)日：2011-06-16

申请号：US12635005

申请日：2009-12-10

申请人： John Zahurak ,  Sanh D. Tang ,  Gurtej S. Sandhu

发明人： John Zahurak ,  Sanh D. Tang ,  Gurtej S. Sandhu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/823487 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/105 ,  H01L27/24 ,  H01L29/66666 ,  H01L29/7827

摘要： Methods of forming an array of memory cells and memory cells that have pillars. Individual pillars can have a semiconductor post formed of a bulk semiconductor material and a sacrificial cap on the semiconductor post. Source regions can be between columns of the pillars, and gate lines extend along a column of pillars and are spaced apart from corresponding source regions. Each gate line surrounds a portion of the semiconductor posts along a column of pillars. The sacrificial cap structure can be selectively removed to thereby form self-aligned openings that expose a top portion of corresponding semiconductor posts. Individual drain contacts formed in the self-aligned openings are electrically connected to corresponding semiconductor posts.

摘要翻译： 形成具有支柱的存储器单元阵列和存储单元阵列的方法。 单个柱可以具有由半导体柱上的体半导体材料和牺牲帽形成的半导体柱。 源区可以在柱的列之间，并且栅极线沿着柱柱延伸并且与相应的源极区域间隔开。 每个栅极线沿着一列柱围绕半导体柱的一部分。 可以选择性地去除牺牲帽结构，从而形成露出相应半导体柱的顶部的自对准开口。 形成在自对准开口中的单独的漏极触点电连接到相应的半导体柱。