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公开(公告)号：US20050198459A1
公开(公告)日：2005-09-08
申请号：US10795037
申请日：2004-03-04
申请人： Zohar Bogin , Tuong Trieu , Sarath Kotamreddy , Jayesh Laddha
发明人： Zohar Bogin , Tuong Trieu , Sarath Kotamreddy , Jayesh Laddha
IPC分类号： G06F12/00
CPC分类号： G06F5/06
摘要： A method and apparatus for open loop buffer allocation. In one embodiment, the method includes loading requested data within a buffer according to a load rate. Concurrent with the loading of data within the buffer, the data is forwarded from the buffer according to drain rate. In situations where the load rate exceeds the drain rate, read requests may be throttled according to an approximate buffer capacity level to prohibit buffer overflow. In one embodiment, a rate for issuing data requests, for example, to memory, is regulated according to a predetermined buffer accumulation rate. Accordingly, in one embodiment, the open loop allocation scheme reduces latency while enabling sustained read streaming with a minimal size read buffer. Other embodiments are described and claimed.
摘要翻译： 一种用于开环缓冲区分配的方法和装置。 在一个实施例中，该方法包括根据负载速率在缓冲器中加载所请求的数据。 与缓冲区内的数据加载一起，数据根据流失速率从缓冲区转发。 在负载率超过排放速率的情况下，读取请求可能会根据大约缓冲区容量限制，以禁止缓冲区溢出。 在一个实施例中，根据预定的缓冲器累积速率来调节用于发布数据请求（例如，存储器）的速率。 因此，在一个实施例中，开环分配方案减少等待时间，同时以最小尺寸的读缓冲器实现持续的读取流。 描述和要求保护其他实施例。
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公开(公告)号：US07180520B2
公开(公告)日：2007-02-20
申请号：US10795939
申请日：2004-03-08
申请人： Sarath Kotamreddy , Tuong Trieu
发明人： Sarath Kotamreddy , Tuong Trieu
CPC分类号： G06F13/1689
摘要： According to one embodiment a chipset is disclosed. The chipset includes a graphics accelerator, a memory controller and a queue mechanism. The queue mechanism includes a first functional unit block (FUB) coupled to the graphics accelerator, and a second FUB coupled to the memory controller.
摘要翻译： 根据一个实施例，公开了一种芯片组。 该芯片组包括图形加速器，存储器控制器和队列机制。 队列机构包括耦合到图形加速器的第一功能单元块（FUB）和耦合到存储器控制器的第二FUB。
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公开(公告)号：US20050195201A1
公开(公告)日：2005-09-08
申请号：US10795939
申请日：2004-03-08
申请人： Sarath Kotamreddy , Tuong Trieu
发明人： Sarath Kotamreddy , Tuong Trieu
CPC分类号： G06F13/1689
摘要： According to one embodiment a chipset is disclosed. The chipset includes a graphics accelerator, a memory controller and a queue mechanism. The queue mechanism includes a first functional unit block (FUB) coupled to the graphics accelerator, and a second FUB coupled to the memory controller.
摘要翻译： 根据一个实施例，公开了一种芯片组。 该芯片组包括图形加速器，存储器控制器和队列机制。 队列机构包括耦合到图形加速器的第一功能单元块（FUB）和耦合到存储器控制器的第二FUB。
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4.发明申请公开(公告)号：US20050141601A1
公开(公告)日：2005-06-30
申请号：US10749429
申请日：2003-12-31
申请人： Lyonel Renaud , Sarath Kotamreddy
发明人： Lyonel Renaud , Sarath Kotamreddy
CPC分类号： G06F13/4086 , G06F2213/0026
摘要： An integrated circuit (IC) device that has an analog front end with an I/O buffer is reset. The I/O buffer has a driver circuit to transmit a stream of information over a serial point to point link, and a receiver circuit to receive a stream of information over the link. Digitally-controllable transmission line terminations are provided for the driver and receiver circuits, respectively. A digitally-controllable reference signal level is also provided for the I/O buffer. A number of impedance matching compensation values are automatically calibrated against one or more reference resistors, by calibrating a first value and then a second value, and a third value. These calibrated values are automatically applied to set the reference signal level, driver termination, and receiver termination, respectively. Other embodiments are also described and claimed.
摘要翻译： 具有模拟前端和I / O缓冲器的集成电路（IC）器件被复位。 I / O缓冲器具有用于通过串行点对点链路传输信息流的驱动器电路，以及用于通过链路接收信息流的接收器电路。 分别为驱动器和接收器电路提供数字可控的传输线终端。 还为I / O缓冲器提供数字可控参考信号电平。 多个阻抗匹配补偿值通过校准第一值，然后校准第二值和第三值，针对一个或多个参考电阻自动校准。 这些校准值将自动应用于分别设置参考信号电平，驱动器终端和接收器端接。 还描述和要求保护其他实施例。
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5.发明授权公开(公告)号：US07321613B2
公开(公告)日：2008-01-22
申请号：US10749429
申请日：2003-12-31
申请人： Lyonel Renaud , Sarath Kotamreddy
发明人： Lyonel Renaud , Sarath Kotamreddy
CPC分类号： G06F13/4086 , G06F2213/0026
摘要： An integrated circuit (IC) device that has an analog front end with an I/O buffer is reset. The I/O buffer has a driver circuit to transmit a stream of information over a serial point to point link, and a receiver circuit to receive a stream of information over the link. Digitally-controllable transmission line terminations are provided for the driver and receiver circuits, respectively. A digitally-controllable reference signal level is also provided for the I/O buffer. A number of impedance matching compensation values are automatically calibrated against one or more reference resistors, by calibrating a first value and then a second value, and a third value. These calibrated values are automatically applied to set the reference signal level, driver termination, and receiver termination, respectively. Other embodiments are also described and claimed.
摘要翻译： 具有模拟前端和I / O缓冲器的集成电路（IC）器件被复位。 I / O缓冲器具有用于通过串行点对点链路传输信息流的驱动器电路，以及用于通过链路接收信息流的接收器电路。 分别为驱动器和接收器电路提供数字可控的传输线终端。 还为I / O缓冲器提供数字可控参考信号电平。 多个阻抗匹配补偿值通过校准第一值，然后校准第二值和第三值，针对一个或多个参考电阻自动校准。 这些校准值将自动应用于分别设置参考信号电平，驱动器终端和接收器端接。 还描述和要求保护其他实施例。
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6.发明申请Buffer management via non-data symbol processing for a point to point link 审中-公开通过点对点链接的非数据符号处理进行缓冲管理公开(公告)号：US20050144341A1
公开(公告)日：2005-06-30
申请号：US10750013
申请日：2003-12-31
申请人： Daren Schmidt , David Puffer , Sarath Kotamreddy , Lyonel Renaud
发明人： Daren Schmidt , David Puffer , Sarath Kotamreddy , Lyonel Renaud
CPC分类号： G06F5/14
摘要： A number of symbols are received in a first integrated circuit (IC) device, where these symbols have been transmitted by a second IC device and are received over a serial point to point link. These symbols include a non-data sequence that has been inserted into a data sequence by the second device. The symbols are loaded into a buffer. The data sequence and some of the non-data sequence is unloaded from the buffer, according to a changing unload pointer. To prevent overflow of the buffer, and in response to detecting the non-data sequence, the unload pointer is changed by more than one entry so that a non-data symbol of the non-data sequence as loaded in the buffer is skipped while unloading from the buffer. In another embodiment, to prevent underflow of the buffer, the unload pointer is stalled at an entry of the buffer that contains a non-data symbol while unloading. Other embodiments are also described and claimed.
摘要翻译： 在第一集成电路（IC）装置中接收多个符号，其中这些符号已由第二IC器件传输并通过串行点对点链接接收。 这些符号包括已被第二设备插入到数据序列中的非数据序列。 符号被加载到缓冲区。 根据改变的卸载指针，数据序列和一些非数据序列从缓冲区中卸载。 为了防止缓冲器的溢出，并且响应于检测到非数据序列，卸载指针由多个条目改变，使得在卸载期间跳过加载在缓冲器中的非数据序列的非数据符号 从缓冲区。 在另一个实施例中，为了防止缓冲器的下溢，卸载指针在卸载期间在包含非数据符号的缓冲器的条目处被停止。 还描述和要求保护其他实施例。
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公开(公告)号：US20050144487A1
公开(公告)日：2005-06-30
申请号：US10749619
申请日：2003-12-30
CPC分类号： G06F1/3253 , G06F1/3203 , Y02D10/151
摘要： A transmitting device and a receiving device are coupled together via an interconnect. An electrical idle ordered set is received at the receiving device power management unit after having been transmitted by the transmitting device and received at the input pins of the receiving device and moving through the receiver logic pipeline. At the time the electrical idle ordered set has been recognized at the end of the receiver logic pipeline, the power management unit checks for activity on the interconnect. If there is no activity on the interconnect, then the power management unit causes the receiving device to enter a low power state where the receiver circuitry (input buffers) is turned off. If there is activity on the interconnect when the electrical idle ordered set is received at the power management unit, then the power management unit does not cause the receiver circuitry to be turned off.
摘要翻译： 发送装置和接收装置通过互连耦合在一起。 在接收设备电源管理单元已经被发送设备发送并在接收设备的输入引脚处接收并且通过接收机逻辑管线移动之后，接收到电气空闲有序集合。 在接收机逻辑流水线末端已经识别到电气空闲有序集的时候，电源管理单元检查互连上的活动。 如果互连上没有活动，则电源管理单元使接收设备进入接收机电路（输入缓冲器）关闭的低功率状态。 如果在电力管理单元处接收到电气空闲有序集合时在互连上存在活动，则电源管理单元不会使接收器电路关闭。
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公开(公告)号：US20050144342A1
公开(公告)日：2005-06-30
申请号：US10750081
申请日：2003-12-31
CPC分类号： G06F13/385 , H04L7/042
摘要： A stream of bits are received in a first integrated circuit (IC) device, where the stream represents a sequence of symbols transmitted by a second IC device over a serial point to point link that couples the two devices. First and second M-bit sections of the stream are compared to a non-data symbol. The second M-bit section is offset by one bit in the stream relative to the first section. If there is a match between the first section and the non-data symbol, then a flag indicating symbol alignment is asserted. Each of multiple, consecutive, non overlapping M-bit sections that follow the first section are then to be treated as separate symbols. Other embodiments are also described and claimed.
摘要翻译： 在第一集成电路（IC）设备中接收比特流，其中流表示由第二IC设备通过串联点对点链路发送的符号序列，所述串行点对点链路耦合两个设备。 流的第一和第二M位部分与非数据符号进行比较。 第二M位部分相对于第一部分在流中偏移一位。 如果在第一部分和非数据符号之间存在匹配，则表示符号对齐的标志被断言。 随后的第一部分之后的多个，连续的，非重叠的M位部分中的每一个然后将被视为单独的符号。 还描述和要求保护其他实施例。
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9.发明申请Lane to lane deskewing via non-data symbol processing for a serial point to point link 失效通过非串行点对点链接的非数据符号处理对通道进行歪斜校正公开(公告)号：US20050141661A1
公开(公告)日：2005-06-30
申请号：US10749721
申请日：2003-12-31
CPC分类号： H04L25/14 , G06F13/385 , H04L49/90
摘要： Multiple symbol sequences that have been transmitted in parallel using the same transmit clock over a serial point to point link are received. Each symbol sequence includes an instance of a first, non-data symbol. The multiple symbol sequences are buffered and the number of times an instance of a second, non-data symbol that occurs in one of the symbol sequences is changed. A first deskew process is performed, followed by a second deskew process. The first deskew process aligns an instance of the first non-data symbol in every one of the buffered symbol sequences. The second deskew process equalizes the number of instances of the second non-data symbol that follow an instance of the first non-data symbol in every one of the symbol sequences. Other embodiments are also described and claimed.
摘要翻译： 接收到通过串行点对点链路使用相同传输时钟并行发送的多个符号序列。 每个符号序列包括第一非数据符号的实例。 缓冲多个符号序列，并且发生在符号序列之一中的第二非数据符号的实例的次数被改变。 执行第一个偏移过程，然后进行第二个偏移处理。 第一个偏移校正过程对齐每个缓冲符号序列中的第一个非数据符号的一个实例。 第二个偏移校正过程使每个符号序列中的第一非数据符号的实例之后的第二非数据符号的实例的数量相等。 还描述和要求保护其他实施例。
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10.发明申请LANE TO LANE DESKEWING VIA NON-DATA SYMBOL PROCESSING FOR A SERIAL POINT TO POINT LINK 有权通过无线数据符号处理方式来连接点到链路的LANE到LANE DESKING公开(公告)号：US20110066771A1
公开(公告)日：2011-03-17
申请号：US12948103
申请日：2010-11-17
IPC分类号： G06F5/00
CPC分类号： H04L25/14 , G06F13/385 , H04L49/90
摘要： Multiple symbol sequences that have been transmitted in parallel using the same transmit clock over a serial point to point link are received. Each symbol sequence includes an instance of a first, non-data symbol. The multiple symbol sequences are buffered and the number of times an instance of a second, non-data symbol that occurs in one of the symbol sequences is changed. A first deskew process is performed, followed by a second deskew process. The first deskew process aligns an instance of the first non-data symbol in every one of the buffered symbol sequences. The second deskew process equalizes the number of instances of the second non-data symbol that follow an instance of the first non-data symbol in every one of the symbol sequences. Other embodiments are also described and claimed.
摘要翻译： 接收到通过串行点对点链路使用相同传输时钟并行发送的多个符号序列。 每个符号序列包括第一非数据符号的实例。 缓冲多个符号序列，并且发生在符号序列之一中的第二非数据符号的实例的次数被改变。 执行第一个偏移过程，然后进行第二个偏移处理。 第一个偏移校正过程对齐每个缓冲符号序列中的第一个非数据符号的一个实例。 第二个偏移校正过程使每个符号序列中的第一非数据符号的实例之后的第二非数据符号的实例的数量相等。 还描述和要求保护其他实施例。
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