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1.发明申请LANE TO LANE DESKEWING VIA NON-DATA SYMBOL PROCESSING FOR A SERIAL POINT TO POINT LINK 有权通过无线数据符号处理方式来连接点到链路的LANE到LANE DESKING公开(公告)号：US20110066771A1
公开(公告)日：2011-03-17
申请号：US12948103
申请日：2010-11-17
IPC分类号： G06F5/00
CPC分类号： H04L25/14 , G06F13/385 , H04L49/90
摘要： Multiple symbol sequences that have been transmitted in parallel using the same transmit clock over a serial point to point link are received. Each symbol sequence includes an instance of a first, non-data symbol. The multiple symbol sequences are buffered and the number of times an instance of a second, non-data symbol that occurs in one of the symbol sequences is changed. A first deskew process is performed, followed by a second deskew process. The first deskew process aligns an instance of the first non-data symbol in every one of the buffered symbol sequences. The second deskew process equalizes the number of instances of the second non-data symbol that follow an instance of the first non-data symbol in every one of the symbol sequences. Other embodiments are also described and claimed.
摘要翻译： 接收到通过串行点对点链路使用相同传输时钟并行发送的多个符号序列。 每个符号序列包括第一非数据符号的实例。 缓冲多个符号序列，并且发生在符号序列之一中的第二非数据符号的实例的次数被改变。 执行第一个偏移过程，然后进行第二个偏移处理。 第一个偏移校正过程对齐每个缓冲符号序列中的第一个非数据符号的一个实例。 第二个偏移校正过程使每个符号序列中的第一非数据符号的实例之后的第二非数据符号的实例的数量相等。 还描述和要求保护其他实施例。
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2.发明申请LANE TO LANE DESKEWING VIA NON-DATA SYMBOL PROCESSING FOR A SERIAL POINT TO POINT LINK 有权通过无线数据符号处理方式来连接点到链路的LANE到LANE DESKING公开(公告)号：US20090307394A1
公开(公告)日：2009-12-10
申请号：US12544178
申请日：2009-08-19
IPC分类号： G06F13/00
CPC分类号： H04L25/14 , G06F13/385 , H04L49/90
摘要： Multiple symbol sequences that have been transmitted in parallel using the same transmit clock over a serial point to point link are received. Each symbol sequence includes an instance of a first, non-data symbol. The multiple symbol sequences are buffered and the number of times an instance of a second, non-data symbol that occurs in one of the symbol sequences is changed. A first deskew process is performed, followed by a second deskew process. The first deskew process aligns an instance of the first non-data symbol in every one of the buffered symbol sequences. The second deskew process equalizes the number of instances of the second non-data symbol that follow an instance of the first non-data symbol in every one of the symbol sequences. Other embodiments are also described and claimed.
摘要翻译： 接收到通过串行点对点链路使用相同传输时钟并行发送的多个符号序列。 每个符号序列包括第一非数据符号的实例。 缓冲多个符号序列，并且发生在符号序列之一中的第二非数据符号的实例的次数被改变。 执行第一个偏移过程，然后进行第二个偏移处理。 第一个偏移校正过程对齐每个缓冲符号序列中的第一个非数据符号的一个实例。 第二个偏移校正过程使每个符号序列中的第一非数据符号的实例之后的第二非数据符号的实例的数量相等。 还描述和要求保护其他实施例。
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3.发明授权Lane to lane deskewing via non-data symbol processing for a serial point to point link 失效通过非串行点对点链接的非数据符号处理对通道进行歪斜校正公开(公告)号：US07631118B2
公开(公告)日：2009-12-08
申请号：US10749721
申请日：2003-12-31
CPC分类号： H04L25/14 , G06F13/385 , H04L49/90
摘要： Multiple symbol sequences that have been transmitted in parallel using the same transmit clock over a serial point to point link are received. Each symbol sequence includes an instance of a first, non-data symbol. The multiple symbol sequences are buffered and the number of times an instance of a second, non-data symbol that occurs in one of the symbol sequences is changed. A first deskew process is performed, followed by a second deskew process. The first deskew process aligns an instance of the first non-data symbol in every one of the buffered symbol sequences. The second deskew process equalizes the number of instances of the second non-data symbol that follow an instance of the first non-data symbol in every one of the symbol sequences. Other embodiments are also described and claimed.
摘要翻译： 接收到通过串行点对点链路使用相同传输时钟并行发送的多个符号序列。 每个符号序列包括第一非数据符号的实例。 缓冲多个符号序列，并且发生在符号序列之一中的第二非数据符号的实例的次数被改变。 执行第一个偏移过程，然后进行第二个偏移处理。 第一个偏移校正过程对齐每个缓冲符号序列中的第一个非数据符号的一个实例。 第二个偏移校正过程使每个符号序列中的第一非数据符号的实例之后的第二非数据符号的实例的数量相等。 还描述和要求保护其他实施例。
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公开(公告)号：US07339995B2
公开(公告)日：2008-03-04
申请号：US10750081
申请日：2003-12-31
IPC分类号： H04B14/04
CPC分类号： G06F13/385 , H04L7/042
摘要： A stream of bits are received in a first integrated circuit (IC) device, where the stream represents a sequence of symbols transmitted by a second IC device over a serial point to point link that couples the two devices. First and second M-bit sections of the stream are compared to a non-data symbol. The second M-bit section is offset by one bit in the stream relative to the first section. If there is a match between the first section and the non-data symbol, then a flag indicating symbol alignment is asserted. Each of multiple, consecutive, non overlapping M-bit sections that follow the first section are then to be treated as separate symbols. Other embodiments are also described and claimed.
摘要翻译： 在第一集成电路（IC）设备中接收比特流，其中流表示由第二IC设备通过串联点对点链路发送的符号序列，所述串行点对点链路耦合两个设备。 流的第一和第二M位部分与非数据符号进行比较。 第二M位部分相对于第一部分在流中偏移一位。 如果在第一部分和非数据符号之间存在匹配，则表示符号对齐的标志被断言。 随后的第一部分之后的多个，连续的，非重叠的M位部分中的每一个然后将被视为单独的符号。 还描述和要求保护其他实施例。
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公开(公告)号：US07913001B2
公开(公告)日：2011-03-22
申请号：US12544178
申请日：2009-08-19
CPC分类号： H04L25/14 , G06F13/385 , H04L49/90
摘要： Multiple symbol sequences that have been transmitted in parallel using the same transmit clock over a serial point to point link are received. Each symbol sequence includes an instance of a first, non-data symbol. The multiple symbol sequences are buffered and the number of times an instance of a second, non-data symbol that occurs in one of the symbol sequences is changed. A first deskew process is performed, followed by a second deskew process. The first deskew process aligns an instance of the first non-data symbol in every one of the buffered symbol sequences. The second deskew process equalizes the number of instances of the second non-data symbol that follow an instance of the first non-data symbol in every one of the symbol sequences. Other embodiments are also described and claimed.
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6.发明授权Lane to lane deskewing via non-data symbol processing for a serial point to point link 有权通过非串行点对点链接的非数据符号处理对通道进行歪斜校正公开(公告)号：US07979608B2
公开(公告)日：2011-07-12
申请号：US12948103
申请日：2010-11-17
CPC分类号： H04L25/14 , G06F13/385 , H04L49/90
摘要： Multiple symbol sequences that have been transmitted in parallel using the same transmit clock over a serial point to point link are received. Each symbol sequence includes an instance of a first, non-data symbol. The multiple symbol sequences are buffered and the number of times an instance of a second, non-data symbol that occurs in one of the symbol sequences is changed. A first deskew process is performed, followed by a second deskew process. The first deskew process aligns an instance of the first non-data symbol in every one of the buffered symbol sequences. The second deskew process equalizes the number of instances of the second non-data symbol that follow an instance of the first non-data symbol in every one of the symbol sequences. Other embodiments are also described and claimed.
摘要翻译： 接收到通过串行点对点链路使用相同传输时钟并行发送的多个符号序列。 每个符号序列包括第一非数据符号的实例。 缓冲多个符号序列，并且发生在符号序列之一中的第二非数据符号的实例的次数被改变。 执行第一个偏移过程，然后进行第二个偏移处理。 第一个偏移校正过程对齐每个缓冲符号序列中的第一个非数据符号的一个实例。 第二个偏移校正过程使每个符号序列中的第一非数据符号的实例之后的第二非数据符号的实例的数量相等。 还描述和要求保护其他实施例。
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公开(公告)号：US07178045B2
公开(公告)日：2007-02-13
申请号：US10749619
申请日：2003-12-30
CPC分类号： G06F1/3253 , G06F1/3203 , Y02D10/151
摘要： A transmitting device and a receiving device are coupled together via an interconnect. An electrical idle ordered set is received at the receiving device power management unit after having been transmitted by the transmitting device and received at the input pins of the receiving device and moving through the receiver logic pipeline. At the time the electrical idle ordered set has been recognized at the end of the receiver logic pipeline, the power management unit checks for activity on the interconnect. If there is no activity on the interconnect, then the power management unit causes the receiving device to enter a low power state where the receiver circuitry (input buffers) is turned off. If there is activity on the interconnect when the electrical idle ordered set is received at the power management unit, then the power management unit does not cause the receiver circuitry to be turned off.
摘要翻译： 发送装置和接收装置通过互连耦合在一起。 在接收设备电源管理单元已经被发送设备发送并在接收设备的输入引脚处接收并且通过接收机逻辑管线移动之后，接收到电气空闲有序集合。 在接收机逻辑流水线末端已经识别到电气空闲有序集的时候，电源管理单元检查互连上的活动。 如果互连上没有活动，则电源管理单元使接收设备进入接收机电路（输入缓冲器）关闭的低功率状态。 如果在电力管理单元处接收到电气空闲有序集合时在互连上存在活动，则电源管理单元不会使接收器电路关闭。
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公开(公告)号：US07116331B1
公开(公告)日：2006-10-03
申请号：US09644967
申请日：2000-08-23
申请人： Brian D. Possley , David M. Puffer , Kurt B. Robinson , Ray Askew , James S. Chapple , Thomas E. Dever, II
发明人： Brian D. Possley , David M. Puffer , Kurt B. Robinson , Ray Askew , James S. Chapple , Thomas E. Dever, II
IPC分类号： G06F13/14
摘要： A memory controller hub includes a graphics subsystem adapted to perform graphics operations on data, and interface circuitry adapted selectively to couple the graphics subsystem to a local memory through electrical connectors and to couple the memory controller hub to a graphics controller through the electrical connectors.
摘要翻译： 存储器控制器集线器包括适于对数据执行图形操作的图形子系统，以及适于选择性地通过电连接器将图形子系统耦合到本地存储器并且通过电连接器将存储器控制器集线器耦合到图形控制器的接口电路。
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9.发明授权Method for utilizing a single multiplex address bus between DRAM, SRAM and ROM 失效在DRAM，SRAM和ROM之间利用单个复用地址总线的方法
公开(公告)号：US5901298A
公开(公告)日：1999-05-04
申请号：US726700
申请日：1996-10-07
CPC分类号： G06F13/4243
摘要： A memory interface device for interfacing between the local bus and a memory bus. The memory bus is coupled to a static memory and a dynamic memory. The interface device includes first and second internal buses coupled to a selecting device. The selecting device selectively couples one of the first and second internal buses to the memory bus. The memory interface device further includes an interface control unit having an input coupled to the local bus for receiving address and control signals. The interface control unit further has an output, coupled to the first internal bus for generating gating each data transfer in the burst in response to the address and control signals.
摘要翻译： 用于在本地总线和存储器总线之间进行接口的存储器接口装置。 存储器总线耦合到静态存储器和动态存储器。 接口设备包括耦合到选择设备的第一和第二内部总线。 选择装置将第一和第二内部总线中的一个选择性地耦合到存储器总线。 存储器接口设备还包括接口控制单元，其具有耦合到本地总线的输入，用于接收地址和控制信号。 接口控制单元还具有耦合到第一内部总线的输出，用于响应于地址和控制信号而在脉冲串中产生门控每个数据传输。
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公开(公告)号：US07327370B2
公开(公告)日：2008-02-05
申请号：US11174662
申请日：2005-07-06
申请人： Brian D. Possley , David M. Puffer , Kurt B. Robinson , Ray Askew , James S. Chapple , Thomas E. Dever, II
发明人： Brian D. Possley , David M. Puffer , Kurt B. Robinson , Ray Askew , James S. Chapple , Thomas E. Dever, II
摘要： A memory controller hub includes a graphics subsystem adapted to perform graphics operations on data, and interface circuitry adapted selectively to couple the graphics subsystem to a local memory through electrical connectors and to couple the memory controller hub to a graphics controller through the electrical connectors.
摘要翻译： 存储器控制器集线器包括适于对数据执行图形操作的图形子系统，以及适于选择性地通过电连接器将图形子系统耦合到本地存储器并且通过电连接器将存储器控制器集线器耦合到图形控制器的接口电路。
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