公开(公告)号：US08390483B2

公开(公告)日：2013-03-05

申请号：US13097547

申请日：2011-04-29

申请人： Satoru Higashino

发明人： Satoru Higashino

IPC分类号： H03M7/00

CPC分类号： G11B20/1426 ,  G11B7/24044 ,  G11B20/10111 ,  G11B20/1012 ,  G11B20/1024 ,  G11B20/10277 ,  G11B2007/0009 ,  G11B2007/0013 ,  G11B2020/1469 ,  G11B2220/235 ,  G11B2220/2537 ,  H03M5/145

摘要： A coding apparatus includes a transform table in which with regard to data words of m bits and code words of n bits where n and m are both integers and also n>m is established, 2m pieces of code words selected to have a tendency that the number of symbols “1” is small among the 2n pieces of code words of n bits are associated with the 2m pieces of data words of m bits and a coding unit that encodes input data words of m bits on the basis of the transform table.

摘要翻译： 编码装置包括变换表，其中对于m位的数据字和n位的码字，其中n和m都是整数，并且还建立n> m，所选择的2m个码字具有 n位的2n个码字中的符号数1小，与m位的2m个数据字相关联，编码单位根据变换表对m位的输入数据字进行编码。

公开(公告)号：US08027423B2

公开(公告)日：2011-09-27

申请号：US11581238

申请日：2006-10-16

申请人： Satoru Higashino

发明人： Satoru Higashino

IPC分类号： H03D3/24

CPC分类号： H04L7/0331

摘要： A synchronizing apparatus, which controls, by a PLL circuit, a sampling clock to be used to sample input data and synchronizes a phase of the sampling clock with a target phase that is desirable for sampling the input data, includes: phase error detection means for detecting a phase error from sampling data and the sampling clock, the sampling data being sampled from the input data at timing of the sampling clock; frequency error detection means for detecting, based on a differential coefficient obtained as a result of detecting the phase error, a frequency error; and frequency correction means for correcting a frequency of the sampling clock such that the detected frequency error becomes close to zero by adding a frequency correction value to an integral term of a loop filter of the PLL circuit, the frequency correction value being calculated based on the frequency error.

摘要翻译： 一种同步装置，其由PLL电路控制用于采样输入数据的采样时钟，并将采样时钟的相位与期望用于采样输入数据的目标相位同步，包括：相位误差检测装置，用于 从采样数据和采样时钟检测相位误差，采样数据在采样时钟的定时从输入数据中采样; 频率误差检测装置，用于根据作为检测相位误差的结果获得的微分系数检测频率误差; 以及频率校正装置，用于通过将频率校正值与PLL电路的环路滤波器的积分项相加来校正采样时钟的频率，使得所检测的频率误差变得接近于零，所述频率校正值基于 频率误差。

公开(公告)号：US20060083337A1

公开(公告)日：2006-04-20

申请号：US11250431

申请日：2005-10-17

申请人： Satoru Higashino

发明人： Satoru Higashino

IPC分类号： H03D1/00

CPC分类号： H03M13/6343 ,  H03M13/39 ,  H03M13/3961 ,  H03M13/41 ,  H03M13/6511 ,  H03M13/6586

摘要： A decoder including a Viterbi decoding section for Viterbi-decoding data and a fixed delay tree search decoding section for fixed-delay-tree-search-decoding the data includes a metric calculation circuit used by both the Viterbi decoding section and the fixed delay tree search decoding section.

公开(公告)号：US20050213652A1

公开(公告)日：2005-09-29

申请号：US11058104

申请日：2005-02-15

申请人： Satoru Higashino

发明人： Satoru Higashino

IPC分类号： G11B20/10 ,  H03K5/159

CPC分类号： G11B20/10009 ,  G11B20/10046 ,  G11B20/10055 ,  G11B20/10296

摘要： For a waveform containing a partial response and distortion in only the leading-edge portion of inter-symbol interference (ISI) of a waveform equalized by a prior-stage feedforward filter (FFF) so as to satisfy causality, equalization that does not consider postcursor ISI subsequent to the partial response is performed; a feedback filter (FBF) uses a determination result of a decoding device to generate a response for the distortion of the partial response portion and the postcursor ISI; and the result is subtracted from an FFF output delayed by the amount of determination delay to create a desired partial response waveform. As a method for equalization that satisfies causality, a least mean square algorithm is applied to the partial response waveform generated as described above.

摘要翻译： 对于仅包含由前级前馈滤波器（FFF）均衡的波形的符号间干扰（ISI）的前沿部分的部分响应和失真的波形，以满足因果关系，不考虑后置的均衡 执行部分响应之后的ISI; 反馈滤波器（FBF）使用解码装置的确定结果来产生对部分响应部分和后端ISI的失真的响应; 并且从延迟了确定延迟量的FFF输出中减去结果以产生期望的部分响应波形。 作为满足因果关系的均衡方法，将最小均方算法应用于如上所述生成的部分响应波形。

公开(公告)号：US6163421A

公开(公告)日：2000-12-19

申请号：US305932

申请日：1999-05-05

申请人： Yoshihide Shinpuku ,  Hiroyuki Ino ,  Satoru Higashino

发明人： Yoshihide Shinpuku ,  Hiroyuki Ino ,  Satoru Higashino

IPC分类号： G11B5/008 ,  G11B5/012 ,  G11B5/09 ,  G11B20/10

CPC分类号： G11B20/10175 ,  G11B5/0086 ,  G11B5/012 ,  G11B5/09 ,  G11B20/10009

摘要： The present invention relates to an apparatus for azimuth-recording data on a magnetic recording medium. Heads (13a) and (13b) having azimuth angles different from each other are used and data are recorded on and reproduced from a plurality of adjacent tilted recording tracks on a magnetic tape T. A recording-system encoder (23) converts data to a code sequence in which null points of frequency spectrums are respectively provided at null points of waveform equalization characteristics of partial responses such as PR1, PR4, etc. For example, record-coding using a 8/10MSN code is performed. A reproduction-system equalizing circuit (28) performs waveform equalization based on the partial responses. Further, a data detector (29) detects the data by a Viterbi coding method for executing state transition during which the characteristic of the code sequence is adopted. Azimuth-recording in a narrow track width can be easily achieved while a reduction in effective recording speed due to an increase in the azimuth angle is being controlled.

摘要翻译： 本发明涉及一种在磁记录介质上方位记录数据的装置。 使用具有彼此不同的方位角的头（13a）和（13b），并且将数据记录在磁带T上的多个相邻的倾斜记录轨道上并从其再现。记录系统编码器（23）将数据转换为 在PR1，PR4等部分响应的波形均衡特性的零点分别提供频谱的空点的码序列。例如，使用8 / 10MSN码进行记录编码。 再现系统均衡电路（28）基于部分响应执行波形均衡。 此外，数据检测器（29）通过维特比编码方法检测数据，用于执行代码序列的特性的状态转换。 可以容易地实现窄轨道宽度的方位记录，同时控制由于方位角的增加而导致的有效记录速度的降低。

公开(公告)号：US20110273972A1

公开(公告)日：2011-11-10

申请号：US13097547

申请日：2011-04-29

申请人： Satoru Higashino

发明人： Satoru Higashino

IPC分类号： G11B20/00 ,  H03M7/00

CPC分类号： G11B20/1426 ,  G11B7/24044 ,  G11B20/10111 ,  G11B20/1012 ,  G11B20/1024 ,  G11B20/10277 ,  G11B2007/0009 ,  G11B2007/0013 ,  G11B2020/1469 ,  G11B2220/235 ,  G11B2220/2537 ,  H03M5/145

摘要： A coding apparatus includes a transform table in which with regard to data words of m bits and code words of n bits where n and m are both integers and also n>m is established, 2m pieces of code words selected to have a tendency that the number of symbols “1” is small among the 2n pieces of code words of n bits are associated with the 2m pieces of data words of m bits and a coding unit that encodes input data words of m bits on the basis of the transform table.

摘要翻译： 编码装置包括变换表，其中对于m位的数据字和n位的码字，其中n和m都是整数，并且还建立n> m，所选择的2m个码字具有 符号数“1”在n位的2n个码字中与2比特m比特的数据字相关联，编码单元基于变换表编码m比特的输入数据字。

公开(公告)号：US20070092040A1

公开(公告)日：2007-04-26

申请号：US11581238

申请日：2006-10-16

申请人： Satoru Higashino

发明人： Satoru Higashino

IPC分类号： H03D3/24

CPC分类号： H04L7/0331

摘要： A synchronizing apparatus, which controls, by a PLL circuit, a sampling clock to be used to sample input data and synchronizes a phase of the sampling clock with a target phase that is desirable for sampling the input data, includes: phase error detection means for detecting a phase error from sampling data and the sampling clock, the sampling data being sampled from the input data at timing of the sampling clock; frequency error detection means for detecting, based on a differential coefficient obtained as a result of detecting the phase error, a frequency error; and frequency correction means for correcting a frequency of the sampling clock such that the detected frequency error becomes close to zero by adding a frequency correction value to an integral term of a loop filter of the PLL circuit, the frequency correction value being calculated based on the frequency error.

摘要翻译： 一种同步装置，其由PLL电路控制用于采样输入数据的采样时钟，并将采样时钟的相位与期望用于采样输入数据的目标相位同步，包括：相位误差检测装置，用于 从采样数据和采样时钟检测相位误差，采样数据在采样时钟的定时从输入数据中采样; 频率误差检测装置，用于根据作为检测相位误差的结果获得的微分系数检测频率误差; 以及频率校正装置，用于通过将频率校正值与PLL电路的环路滤波器的积分项相加来校正采样时钟的频率，使得所检测的频率误差变得接近于零，所述频率校正值基于 频率误差。

公开(公告)号：US06622280B1

公开(公告)日：2003-09-16

申请号：US09257861

申请日：1999-02-26

申请人： Satoru Higashino

发明人： Satoru Higashino

IPC分类号： H03M1333

CPC分类号： G11B20/10055 ,  G11B20/10009 ,  G11B20/10296 ,  G11B20/1426 ,  H03M13/33 ,  H03M13/41 ,  H03M13/6331 ,  H03M13/6502

摘要： It is an object to save a circuit scale and simultaneously improve sync-byte pattern detecting performance. A Viterbi detecting circuit executes first the detecting operation without relation to time limitation. A sync-byte detecting circuit detects the sync-byte from the detection result supplied from a path memory built in the Viterbi detecting circuit and also outputs the detected signal to switches and Viterbi detecting circuit in the timing to start detection of user data. The Viterbi circuit initializes (resets) the path memory and path metric corresponding to the detected signal supplied from the sync-byte detecting circuit and also starts subsequently the trellis Viterbi detection accompanied by the time limitation of the trellis path to the data supplied from the switch.

摘要翻译： 其目的是节省电路规模，同时提高同步字节模式检测性能。 维特比检测电路首先执行与时间限制无关的检测操作。 同步字节检测电路根据从维特比检测电路内置的路径存储器提供的检测结果检测同步字节，并且在开始检测用户数据的定时中将检测信号输出到开关和维特比检测电路。 维特比电路对与从同步字节检测电路提供的检测信号相对应的路径存储器和路径度量进行初始化（复位），并随后启动网格维特比检测，伴随着网格路径对从交换机提供的数据的时间限制 。

公开(公告)号：US08724441B2

公开(公告)日：2014-05-13

申请号：US13097478

申请日：2011-04-29

申请人： Satoru Higashino

发明人： Satoru Higashino

IPC分类号： G11B20/14

CPC分类号： H03M7/14 ,  G11B7/00453 ,  G11B7/00781 ,  G11B7/24038 ,  G11B7/24044 ,  G11B20/10111 ,  G11B20/1012 ,  G11B20/10277 ,  G11B20/10296 ,  G11B20/1426 ,  G11B2007/0009 ,  G11B2007/0013 ,  G11B2020/1268 ,  G11B2020/1457 ,  G11B2220/2504

摘要： An encoding device for converting m-bit data words into n-bit (both n and m are integers and 2n≧2m×2) code words includes a first encoding table in which 2m code words selected from the 2n n-bit code words correspond to 2m m-bit data words, a second encoding table in which 2m code words, which do not overlap with the code words in the first encoding table, of the 2n n-bit code words correspond to 2m m-bit data words, and an encoding unit which selects and outputs a code word, in which an absolute value of a code string DSV is smaller, from code words corresponding to the input m-bit data words in the first encoding table and code words corresponding to the input m-bit data words in the second encoding table.

摘要翻译： 用于将m位数据字转换为n位（n和m都是整数，2n≥2m×2）的编码装置包括第一编码表，其中从2n个n位代码字中选择的2m个代码字对应于 到2m m位数据字，其中2n个n位码字中不与第一编码表中的码字重叠的2m码字的2m码字对应于2m m位数据字的第二编码表，以及 从与第一编码表中的输入m位数据字对应的代码字和与输入的m-位对应的代码字中选择并输出代码串DSV的绝对值较小的代码字的编码单元， 第二编码表中的位数据字。

公开(公告)号：US08059017B2

公开(公告)日：2011-11-15

申请号：US11605583

申请日：2006-11-29

申请人： Satoru Higashino

发明人： Satoru Higashino

IPC分类号： H03M7/00

CPC分类号： H03M5/145 ,  G11B20/10083 ,  G11B20/10101 ,  G11B20/10111 ,  G11B20/1426

摘要： A modulation apparatus includes: a modulation section that modulates, in accordance with a correlation table where a data sequence with a predetermined number of bits is associated with a code sequence with a predetermined number of bits, the data sequence into the code sequence to allow a predetermined demodulation section to demodulate the code sequence into the data sequence in accordance with the correlation table, wherein the code sequence is, on NRZI method, a MSN code sequence where a null point of a frequency spectrum on a recording channel or communication channel of the code sequence is matched with a null point of a frequency spectrum of a PR equalized signal including the code sequence and a minimum run length is limited to be greater or equal to one.

摘要翻译： 一种调制装置，包括：调制部，其根据相关表，其中具有预定位数的数据序列与预定位数的码序列相关联，将数据序列调制成码序列，以允许 预定解调部分，用于根据相关表将码序列解调成数据序列，其中码序列是以NRZI方法的MSN码序列，其中在记录信道或通信信道上的频谱的零点 代码序列与包括代码序列的PR均衡信号的频谱的零点匹配，并且最小游程长度被限制为大于或等于1。