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    Integrated circuit device and electronic instrument
    4.
    发明申请
    Integrated circuit device and electronic instrument 审中-公开
    集成电路器件和电子仪器

    公开(公告)号：US20070013635A1

    公开(公告)日：2007-01-18

    申请号：US11477742

    申请日：2006-06-30

    申请人： Satoru Ito ,  Masahiko Moriguchi ,  Kazuhiro Maekawa ,  Noboru Itomi ,  Satoru Kodaira ,  Junichi Karasawa ,  Takashi Kumagai ,  Hisanobu Ishiyama ,  Takashi Fujise

    发明人： Satoru Ito ,  Masahiko Moriguchi ,  Kazuhiro Maekawa ,  Noboru Itomi ,  Satoru Kodaira ,  Junichi Karasawa ,  Takashi Kumagai ,  Hisanobu Ishiyama ,  Takashi Fujise

    IPC分类号： G09G3/36

    CPC分类号： G09G3/3674 ,  G09G3/3685

    摘要： An integrated circuit device includes a data driver block DB, a memory block MB, and a logic circuit block LB. The data driver block DB includes a data driver DR and a buffer circuit BF which buffers a driver control signal from the logic circuit block LB and outputs the buffered driver control signal to the data driver DR. The memory block MB includes a memory cell array MA and a row address decoder RD which selects a wordline. The data driver block DB and the memory block MB are disposed along a direction D1, the buffer circuit BF and the data driver DR are disposed along a direction D2, the row address decoder RD and the memory cell array MA are disposed along the direction D2, and the buffer circuit BF and the row address decoder RD are disposed along the direction D1.

    摘要翻译： 集成电路装置包括数据驱动块DB，存储块MB和逻辑电路块LB。 数据驱动器块DB包括数据驱动器DR和缓冲电路BF，其缓冲来自逻辑电路块LB的驱动器控制信号，并将缓冲的驱动器控制信号输出到数据驱动器DR。 存储块MB包括选择字线的存储单元阵列MA和行地址解码器RD。 数据驱动块DB和存储块MB沿着方向D1设置，缓冲电路BF和数据驱动器DR沿着方向D 2设置，行地址解码器RD和存储单元阵列MA沿着 方向D 2，并且缓冲电路BF和行地址解码器RD沿着方向D1设置。

    Integrated circuit device and electronic instrument
    9.
    发明申请
    Integrated circuit device and electronic instrument 审中-公开
    集成电路器件和电子仪器

    公开(公告)号：US20070001983A1

    公开(公告)日：2007-01-04

    申请号：US11477718

    申请日：2006-06-30

    申请人： Satoru Ito ,  Masahiko Moriguchi ,  Kazuhiro Maekawa ,  Takashi Kumagai ,  Hisanobu Ishiyama ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira

    发明人： Satoru Ito ,  Masahiko Moriguchi ,  Kazuhiro Maekawa ,  Takashi Kumagai ,  Hisanobu Ishiyama ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira

    IPC分类号： G09G3/36

    CPC分类号： G09G3/3688 ,  G09G5/363 ,  G09G2310/027 ,  G09G2320/0276 ,  G11C7/16

    摘要： An integrated circuit device includes a data driver block for driving data lines. The data driver block includes a plurality of subpixel driver cells, each of which outputs a data signal corresponding to image data of one subpixel. When a direction along the long side of the subpixel driver cell is a direction D1 and a direction perpendicular to the first direction is a direction D2, the subpixel driver cells are disposed in the data driver block along the direction D1 and the direction D2. Pads are disposed on the D2 side of the data driver block. A rearrangement wiring region for rearranging the order of pull-out lines of output signals from the subpixel driver cells is provided in the arrangement region of the subpixel driver cells.

    摘要翻译： 集成电路装置包括用于驱动数据线的数据驱动器块。 数据驱动器块包括多个子像素驱动器单元，每个子像素驱动器单元输出与一个子像素的图像数据相对应的数据信号。 当沿着子像素驱动单元的长边的方向是方向D1并且垂直于第一方向的方向是方向D 2时，子像素驱动单元沿方向D1设置在数据驱动器块中，方向 D 2.垫子放置在数据驱动器块的D 2侧。 在子像素驱动器单元的配置区域中设置有用于重新排列来自子像素驱动器单元的输出信号的拉出线的顺序的重排布线区域。