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公开(公告)号:US20120019566A1
公开(公告)日:2012-01-26
申请号:US13137995
申请日:2011-09-23
申请人: Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
发明人: Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
IPC分类号: G09G5/10
CPC分类号: G09G3/3688 , G09G3/2011 , G09G2330/02 , G09G2330/04 , H01L2224/05553
摘要: An integrated circuit device includes first to Nth circuit blocks CB1 to CBN, a first interface region disposed along a fourth side and on the D2 side of the first to Nth circuit blocks CB1 to CBN, and a second interface region disposed along a second side and on the D4 side of the first to Nth circuit blocks CB1 to CBN. A local line LLG formed using a wiring layer lower than an Ith layer is provided between the adjacent circuit blocks as at least one of a signal line and a power supply line. Global lines GLG and GLD formed using the Ith or higher wiring layer are provided along the direction D1 over the circuit block disposed between the nonadjacent circuit blocks as at least one of a signal line and a power supply line.
摘要翻译: 集成电路装置包括第一至第N电路块CB1至CBN,沿第一至第N电路块CB1至CBN的第四侧和第二侧设置的第一接口区域以及沿着第二侧设置的第二接口区域, 在第一至第N电路块CB1至CBN的D4侧。 使用低于第I层的布线层形成的局部线LLG设置在相邻的电路块之间,作为信号线和电源线中的至少一个。 使用第I或更高布线层形成的全局线GLG和GLD沿着方向D1设置在布置在不相邻电路块之间的电路块上,作为信号线和电源线中的至少一个。
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公开(公告)号:US08054710B2
公开(公告)日:2011-11-08
申请号:US11477670
申请日:2006-06-30
申请人: Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
发明人: Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
IPC分类号: G11C8/00
CPC分类号: G09G3/3688 , G09G3/2011 , G09G2330/02 , G09G2330/04 , H01L2224/05553
摘要: An integrated circuit device includes first to Nth circuit blocks CB1 to CBN, a first interface region disposed along a fourth side and on the D2 side of the first to Nth circuit blocks CB1 to CBN, and a second interface region disposed along a second side and on the D4 side of the first to Nth circuit blocks CB1 to CBN. A local line LLG formed using a wiring layer lower than an Ith layer is provided between the adjacent circuit blocks as at least one of a signal line and a power supply line. Global lines GLG and GLD formed using the Ith or higher wiring layer are provided along the direction D1 over the circuit block disposed between the nonadjacent circuit blocks as at least one of a signal line and a power supply line.
摘要翻译: 集成电路装置包括第一至第N电路块CB1至CBN,沿第一至第N电路块CB1至CBN的第四侧和第二侧设置的第一接口区域以及沿着第二侧设置的第二接口区域, 在第一至第N电路块CB1至CBN的D4侧。 使用低于第I层的布线层形成的局部线LLG设置在相邻的电路块之间,作为信号线和电源线中的至少一个。 使用第I或更高布线层形成的全局线GLG和GLD沿着方向D1设置在布置在不相邻电路块之间的电路块上,作为信号线和电源线中的至少一个。
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公开(公告)号:US08547722B2
公开(公告)日:2013-10-01
申请号:US13137995
申请日:2011-09-23
申请人: Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
发明人: Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
IPC分类号: G11C5/06
CPC分类号: G09G3/3688 , G09G3/2011 , G09G2330/02 , G09G2330/04 , H01L2224/05553
摘要: An integrated circuit device includes first to Nth circuit blocks CB1 to CBN, a first interface region disposed along a fourth side and on the D2 side of the first to Nth circuit blocks CB1 to CBN, and a second interface region disposed along a second side and on the D4 side of the first to Nth circuit blocks CB1 to CBN. A local line LLG formed using a wiring layer lower than an Ith layer is provided between the adjacent circuit blocks as at least one of a signal line and a power supply line. Global lines GLG and GLD formed using the Ith or higher wiring layer are provided along the direction D1 over the circuit block disposed between the nonadjacent circuit blocks as at least one of a signal line and a power supply line.
摘要翻译: 集成电路装置包括第一至第N电路块CB1至CBN,沿第一至第N电路块CB1至CBN的第四侧和第二侧设置的第一接口区域以及沿着第二侧设置的第二接口区域, 在第一至第N电路块CB1至CBN的D4侧。 使用低于第I层的布线层形成的局部线LLG设置在相邻的电路块之间,作为信号线和电源线中的至少一个。 使用第I或更高布线层形成的全局线GLG和GLD沿着方向D1设置在布置在不相邻电路块之间的电路块上,作为信号线和电源线中的至少一个。
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公开(公告)号:US20070013635A1
公开(公告)日:2007-01-18
申请号:US11477742
申请日:2006-06-30
申请人: Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
发明人: Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
IPC分类号: G09G3/36
CPC分类号: G09G3/3674 , G09G3/3685
摘要: An integrated circuit device includes a data driver block DB, a memory block MB, and a logic circuit block LB. The data driver block DB includes a data driver DR and a buffer circuit BF which buffers a driver control signal from the logic circuit block LB and outputs the buffered driver control signal to the data driver DR. The memory block MB includes a memory cell array MA and a row address decoder RD which selects a wordline. The data driver block DB and the memory block MB are disposed along a direction D1, the buffer circuit BF and the data driver DR are disposed along a direction D2, the row address decoder RD and the memory cell array MA are disposed along the direction D2, and the buffer circuit BF and the row address decoder RD are disposed along the direction D1.
摘要翻译: 集成电路装置包括数据驱动块DB,存储块MB和逻辑电路块LB。 数据驱动器块DB包括数据驱动器DR和缓冲电路BF,其缓冲来自逻辑电路块LB的驱动器控制信号,并将缓冲的驱动器控制信号输出到数据驱动器DR。 存储块MB包括选择字线的存储单元阵列MA和行地址解码器RD。 数据驱动块DB和存储块MB沿着方向D1设置,缓冲电路BF和数据驱动器DR沿着方向D 2设置,行地址解码器RD和存储单元阵列MA沿着 方向D 2,并且缓冲电路BF和行地址解码器RD沿着方向D1设置。
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公开(公告)号:US20070001982A1
公开(公告)日:2007-01-04
申请号:US11477670
申请日:2006-06-30
申请人: Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
发明人: Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
IPC分类号: G09G3/36
CPC分类号: G09G3/3688 , G09G3/2011 , G09G2330/02 , G09G2330/04 , H01L2224/05553
摘要: An integrated circuit device includes first to Nth circuit blocks CB1 to CBN, a first interface region disposed along a fourth side and on the D2 side of the first to Nth circuit blocks CB1 to CBN, and a second interface region disposed along a second side and on the D4 side of the first to Nth circuit blocks CB1 to CBN. A local line LLG formed using a wiring layer lower than an Ith layer is provided between the adjacent circuit blocks as at least one of a signal line and a power supply line. Global lines GLG and GLD formed using the Ith or higher wiring layer are provided along the direction D1 over the circuit block disposed between the nonadjacent circuit blocks as at least one of a signal line and a power supply line.
摘要翻译: 集成电路装置包括第一至第N电路块CB 1至CBN,沿着第一至第N电路块CB 1至CBN的第四侧和第二侧设置的第一接口区域,以及沿着第二至第N电路块 并且在第一至第N电路块CB 1至CBN的D4侧。 使用低于第I层的布线层形成的局部线LLG设置在相邻的电路块之间,作为信号线和电源线中的至少一个。 使用第I或更高布线层形成的全局线GLG和GLD沿着方向D1设置在布置在不相邻电路块之间的电路块上,作为信号线和电源线中的至少一个。
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公开(公告)号:US20070001886A1
公开(公告)日:2007-01-04
申请号:US11477646
申请日:2006-06-30
申请人: Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
发明人: Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
IPC分类号: H03M1/66
CPC分类号: G09G3/3611 , G09G3/3648 , G09G3/3696 , G09G2360/18
摘要: An integrated circuit device includes a driver macrocell in which a plurality of circuit blocks are integrated into a macrocell. The driver macrocell includes a data driver block DB for driving data lines, a memory block MB which stores image data, and a pad block PDB in which pads for electrically connecting output lines of the data driver block DB with the data lines are disposed. The data driver block DB and the memory block MB are disposed along a direction D1, and the pad block PDB is disposed on the D2 side of the data driver block DB and the memory block MB.
摘要翻译: 集成电路装置包括驱动器宏单元,其中多个电路块集成到宏单元中。 驱动器宏单元包括用于驱动数据线的数据驱动器块DB,存储图像数据的存储器块MB和用于电连接数据驱动器块DB的输出线与数据线的焊盘的焊盘块PDB。 数据驱动块DB和存储块MB沿着方向D1设置,并且焊盘块PDB设置在数据驱动块DB和存储块MB的D 2侧。
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公开(公告)号:US20070013706A1
公开(公告)日:2007-01-18
申请号:US11477647
申请日:2006-06-30
申请人: Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa
发明人: Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa
CPC分类号: G09G3/3685 , G09G2300/0426 , G09G2310/0218 , G09G2310/027 , G09G2310/0275 , G09G2360/12
摘要: Each of RAM blocks provided in a display memory and disposed along a first direction in which bitlines extend includes a sense amplifier circuit which outputs M-bit data upon one wordline selection (M is an integer larger than 1). At least M memory cells are arranged in each of the RAM blocks along a second direction in which wordlines extend. M sense amplifier cells to which M-bit data read from the M memory cells is input are provided in the sense amplifier circuit. L sense amplifier cells of the M sense amplifier cells are disposed at a position corresponding to L memory cells adjacent in the second direction (L is an integer which satisfies 2≦L
摘要翻译: 提供在显示存储器中并沿着位线延伸的第一方向布置的每个RAM块包括读取放大器电路,其在一个字线选择(M是大于1的整数)上输出M位数据。 至少M个存储单元沿着字线延伸的第二方向布置在每个RAM块中。 在读出放大器电路中设置有从M个存储单元读取M位数据的M个读出放大器单元。 M个读出放大器单元的L个读出放大器单元配置在与第二方向相邻的L个存储单元对应的位置(L为满足2 <= L
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公开(公告)号:US20070013687A1
公开(公告)日:2007-01-18
申请号:US11477716
申请日:2006-06-30
申请人: Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa
发明人: Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa
IPC分类号: G09G5/00
CPC分类号: G09G3/20 , G09G2310/027 , G09G2360/18
摘要: An integrated circuit device includes a display memory and a data read control circuit. The data read control circuit controls data reading so that data of pixels corresponding to a plurality of signal lines is read out by N-time reading in one horizontal scan period of a display panel (N is an integer larger than 1). The display memory includes a plurality of sense amplifier cells respectively connected with a plurality of bitlines. L sense amplifier cells (L is an integer larger than 1) respectively connected with the bitlines of L memory cells adjacent in a first direction (wordline direction) in which wordlines extend are disposed along a second direction (bitline direction) in which the bitlines extend.
摘要翻译: 集成电路装置包括显示存储器和数据读取控制电路。 数据读取控制电路控制数据读取,使得通过在显示面板的一个水平扫描周期(N是大于1的整数)中的N次读取来读出与多条信号线相对应的像素的数据。 显示存储器包括分别与多个位线连接的多个读出放大器单元。 分别与字线延伸的第一方向(字线方向)相邻的L个存储单元的位线分别连接的L个读出放大器单元(L是大于1的整数)沿着位线延伸的第二个方向(位线方向) 。
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公开(公告)号:US07782694B2
公开(公告)日:2010-08-24
申请号:US11477716
申请日:2006-06-30
申请人: Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa
发明人: Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa
IPC分类号: G11C7/00
CPC分类号: G09G3/20 , G09G2310/027 , G09G2360/18
摘要: An integrated circuit device includes a display memory and a data read control circuit. The data read control circuit controls data reading so that data of pixels corresponding to a plurality of signal lines is read out by N-time reading in one horizontal scan period of a display panel (N is an integer larger than 1). The display memory includes a plurality of sense amplifier cells respectively connected with a plurality of bitlines. L sense amplifier cells (L is an integer larger than 1) respectively connected with the bitlines of L memory cells adjacent in a first direction (wordline direction) in which wordlines extend are disposed along a second direction (bitline direction) in which the bitlines extend.
摘要翻译: 集成电路装置包括显示存储器和数据读取控制电路。 数据读取控制电路控制数据读取,使得通过在显示面板的一个水平扫描周期(N是大于1的整数)中的N次读取来读出与多条信号线相对应的像素的数据。 显示存储器包括分别与多个位线连接的多个读出放大器单元。 分别与字线延伸的第一方向(字线方向)相邻的L个存储单元的位线分别连接的L个读出放大器单元(L是大于1的整数)沿着位线延伸的第二个方向(位线方向) 。
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公开(公告)号:US07613066B2
公开(公告)日:2009-11-03
申请号:US11477719
申请日:2006-06-30
申请人: Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa
发明人: Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa
IPC分类号: G11C8/00
CPC分类号: G09G3/3685 , G09G2300/0426 , G09G2310/0218 , G09G2310/027 , G09G2360/12
摘要: In an integrated circuit device, a data line driver block which drives data lines of a display panel based on data supplied from a RAM block from which data is read N times (N is an integer larger than one) in one horizontal scan period 1H of the display panel includes first to N-th divided data line driver blocks disposed along a first direction in which bitlines extend. When data supplied from the RAM block is M bits (M is an integer larger than 1) and grayscale of a pixel corresponding to the data line is G bits, each of the first to N-th divided data line driver blocks includes (M/G) (multiple of three) data line driver cells which drive (M/G) data lines. (M/3G) R data line driver cells are provided in a first subdivided driver, (M/3G) G data line driver cells are provided in a second subdivided driver, and (M/3G) B data line driver cells are provided in a third subdivided driver.
摘要翻译: 在集成电路装置中,数据线驱动器模块,其基于从RAM数据块提供的数据驱动显示面板的数据线,数据被读取N次(N为大于1的整数)N 显示面板包括沿位线延伸的第一方向设置的第一至第N分割数据线驱动器块。 当从RAM块提供的数据是M位(M是大于1的整数)并且与数据线相对应的像素的灰度级是G位时,第一至第N划分数据线驱动器块中的每一个包括(M / G)(三个的三个)数据线驱动器单元驱动(M / G)数据线。 (M / 3G)R数据线驱动器单元设置在第一细分驱动器中,(M / 3G)G数据线驱动器单元设置在第二细分驱动器中,并且(M / 3G)B数据线驱动器单元设置在 第三个细分驱动程序。
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