公开(公告)号：US06259494B1

公开(公告)日：2001-07-10

申请号：US09010688

申请日：1998-01-22

申请人： Satoru Kawai ,  Kiyoshi Ozaki ,  Jun Inoue ,  Yoshio Dejima ,  Kenji Okamoto

发明人： Satoru Kawai ,  Kiyoshi Ozaki ,  Jun Inoue ,  Yoshio Dejima ,  Kenji Okamoto

IPC分类号： G01F11345

CPC分类号： G02F1/136259 ,  G02F1/136213 ,  G02F2001/136263 ,  G02F2001/136272

摘要： A repairable integrated thin film transistor matrix substrate includes an insulated substrate, and a plurality of parallel gate bus lines and a plurality of accumulated capacitance bus lines formed on the insulated substrate. Each of the accumulated capacitance bus lines extend parallel to and between a pair of the gate bus lines, and has a plurality of auxiliary capacitance electrodes which extend from it. A first insulated film is provided on the gate and accumulated capacitance bus lines and the auxiliary capacitance electrodes. A plurality of operating films are formed on the first insulated film, and on each of the operating films, a corresponding thin film transistors are provided. At least two of the thin film transistors are electrically connected to each of the gate bus lines. Also included is a plurality of parallel drain bus lines which are provided substantially perpendicular to the gate and the accumulated capacitance bus lines on the first insulated film. Each drain bus line electrically connects at least two of the thin film transistors. In addition, a second insulated film having an opening over each of the thin film transistors is provided on the thin film transistors and the drain bus lines. Further, a plurality of pixel electrodes are provided on the second insulated film, which pixel electrodes being electrically connected to a corresponding one of the transistors via the opening. At least one first portion of at least one of the gate and the drain bus lines overlaps with at least one second portion of at least one of the auxiliary capacitance and the pixel electrodes. A method for repairing the matrix substrate generally includes electrically connecting a conductor to either sides of a defect to act as a bypass.

摘要翻译： 可修复的集成薄膜晶体管矩阵基板包括绝缘基板，以及形成在绝缘基板上的多个平行栅极总线和多个累积电容总线。 每个累积的电容总线平行于一对栅极总线之间延伸，并且具有从其延伸的多个辅助电容电极。 在栅极上设置第一绝缘膜，并且累积电容总线和辅助电容电极。 在第一绝缘膜上形成多个操作膜，并且在每个操作膜上设置相应的薄膜晶体管。 至少两个薄膜晶体管电连接到每个栅极总线。 还包括多个平行的漏极总线，它们大致垂直于第一绝缘膜上的栅极和累积的电容总线。 每个漏极总线线路将至少两个薄膜晶体管电连接。 此外，在薄膜晶体管和漏极总线上设置有在每个薄膜晶体管上具有开口的第二绝缘膜。 此外，多个像素电极设置在第二绝缘膜上，这些像素电极经由开口电连接到相应的一个晶体管。 栅极和漏极总线中的至少一个的至少一个第一部分与辅助电容和像素电极中的至少一个的至少一个第二部分重叠。 用于修复矩阵衬底的方法通常包括将导体电连接到缺陷的任一侧以用作旁路。

公开(公告)号：US06614494B2

公开(公告)日：2003-09-02

申请号：US09861796

申请日：2001-05-21

申请人： Satoru Kawai ,  Kiyoshi Ozaki ,  Jun Inoue ,  Yoshio Dejima ,  Kenji Okamoto

发明人： Satoru Kawai ,  Kiyoshi Ozaki ,  Jun Inoue ,  Yoshio Dejima ,  Kenji Okamoto

IPC分类号： G02F11343

CPC分类号： G02F1/136259 ,  G02F1/136213 ,  G02F2001/136263 ,  G02F2001/136272

摘要： A repairable integrated thin film transistor matrix substrate includes an insulated substrate, and a plurality of parallel gate bus lines and a plurality of accumulated capacitance bus lines formed on the insulated substrate. Each of the accumulated capacitance bus lines extend parallel to and between a pair of the gate bus lines, and has a plurality of auxiliary capacitance electrodes which extend from it. A first insulated film is provided on the gate and accumulated capacitance bus lines and the auxiliary capacitance electrodes. A plurality of operating films are formed on the first insulated film, and on each of the operating films, a corresponding thin film transistors are provided. At least two of the thin film transistors are electrically connected to each of the gate bus lines. Also included is a plurality of parallel drain bus lines which are provided substantially perpendicular to the gate and the accumulated capacitance bus lines on the first insulated film. Each drain bus line electrically connects at least two of the thin film transistors. In addition, a second insulated film having an opening over each of the thin film transistors is provided on the thin film transistors and the drain bus lines. Further, a plurality of pixel electrodes are provided on the second insulated film, which pixel electrodes being electrically connected to a corresponding one of the transistors via the opening. At least one first portion of at least one of the gate and the drain bus lines overlaps with at least one second portion of at least one of the auxiliary capacitance and the pixel electrodes. A method for repairing the matrix substrate generally includes electrically connecting a conductor to either sides of a defect to act as a bypass.

摘要翻译： 可修复的集成薄膜晶体管矩阵基板包括绝缘基板，以及形成在绝缘基板上的多个平行栅极总线和多个累积电容总线。 每个累积的电容总线平行于一对栅极总线之间延伸，并且具有从其延伸的多个辅助电容电极。 在栅极上设置第一绝缘膜，并且累积电容总线和辅助电容电极。 在第一绝缘膜上形成多个操作膜，并且在每个操作膜上设置相应的薄膜晶体管。 至少两个薄膜晶体管电连接到每个栅极总线。 还包括多个平行的漏极总线，它们大致垂直于第一绝缘膜上的栅极和累积的电容总线。 每个漏极总线线路将至少两个薄膜晶体管电连接。 此外，在薄膜晶体管和漏极总线上设置有在每个薄膜晶体管上具有开口的第二绝缘膜。 此外，多个像素电极设置在第二绝缘膜上，这些像素电极经由开口电连接到相应的一个晶体管。 栅极和漏极总线中的至少一个的至少一个第一部分与辅助电容和像素电极中的至少一个的至少一个第二部分重叠。 用于修复矩阵衬底的方法通常包括将导体电连接到缺陷的任一侧以用作旁路。

公开(公告)号：US07763490B2

公开(公告)日：2010-07-27

申请号：US11825973

申请日：2007-07-10

申请人： Yoshio Dejima

发明人： Yoshio Dejima

IPC分类号： H01L29/04 ,  H01L31/0376 ,  H01L31/20 ,  H01L31/036

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/78696

摘要： A stagger type thin film transistor substrate in which each of a source and a drain of a thin film transistor has a laminated structure including a silicon semiconductor layer, a silicon semiconductor layer containing impurities, and a metal layer formed in that order and in which a gate insulator of the thin film transistor is formed on the source and the drain. A pixel electrode is connected to the source via a contact hole made in the gate insulator on the source. Additionally, a gate electrode of the thin film transistor formed on the gate insulator has a laminated structure including two layers of different electrode materials. Finally, the pixel electrode connected to the source is made of an electrode material used in a lower layer of the gate electrode.

摘要翻译： 一种交错型薄膜晶体管基板，其中薄膜晶体管的源极和漏极中的每一个具有包括硅半导体层，含有杂质的硅半导体层和依次形成的金属层的层叠结构，并且其中 在源极和漏极上形成薄膜晶体管的栅极绝缘体。 像素电极通过源极上的栅极绝缘体中形成的接触孔与源极连接。 此外，形成在栅绝缘体上的薄膜晶体管的栅电极具有包括两层不同电极材料的层压结构。 最后，与源极连接的像素电极由在栅电极的下层中使用的电极材料制成。

公开(公告)号：US20120225245A1

公开(公告)日：2012-09-06

申请号：US13505597

申请日：2010-09-15

申请人： Yoshio Dejima

发明人： Yoshio Dejima

IPC分类号： B32B3/10 ,  G03F7/20

CPC分类号： G02F1/13394 ,  G02F1/133516 ,  G02F2001/13396 ,  Y10T428/24331

摘要： Disclosed is a display panel substrate including a spacer that allows adjustment of the height of the spacer without affecting color characteristics of colored patterns. The display panel substrate comprises colored patterns 13r, 13g, and 13b of a prescribed plurality of colors for use in a color display, the colored patterns 13r, 13g, and 13b being made of photosensitive materials; and a spacer 2 having a first subspacer 21, an opening formed in the central portion of the plane direction thereof, and a second subspacer 22, a portion therereof overlaping upon the first subspacer and another portion thereof being fitted upon the opening that is formed on the first subspacer, wherein the first subspacer 21 is formed of the same material as that of one color of the colored patterns 13r, 13g, 13b among the plurality of colored patterns 13r, 13g, and 13b, and the second subspacer 22 is formed of the same material as that of a color of the colored patterns 13r, 13g, and 13b different from that of the first subspacer 21.

摘要翻译： 公开了一种显示面板基板，包括间隔件，其可以调节间隔件的高度而不影响着色图案的颜色特性。 显示面板基板包括用于彩色显示的规定多种颜色的彩色图案13r，13g和13b，彩色图案13r，13g和13b由感光材料制成; 以及间隔件2，具有第一子间隔件21，形成在其平面方向的中心部分中的开口，以及第二子间隔件22，与第一子间隔件重叠的部分，其另一部分安装在形成在 第一子间隔器，其中第一子筛子21由与多个着色图案13r，13g和13b中的着色图案13r，13g，13b的一种颜色相同的材料形成，并且第二子间隔物22由 与与第一子间隔物21不同的着色图案13r，13g和13b的颜色相同的材料。

公开(公告)号：US20070257262A1

公开(公告)日：2007-11-08

申请号：US11825973

申请日：2007-07-10

申请人： Yoshio Dejima

发明人： Yoshio Dejima

IPC分类号： H01L29/04 ,  H01L29/786

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/78696

摘要： A stagger type TFT substrate and a fabrication method therefor in which the number of exposure processes is reduced. A resist pattern is formed in an area on the TFT substrate where a drain bus-line (DB) is to be formed and an area on the TFT substrate where a TFT is to be formed by the use of a half tone mask. Etching is performed with this resist pattern as a mask to form the DB and a channel area for the TFT. In addition, a resist pattern is formed in an area where a gate bus-line (GB) is to be formed and an area where a pixel electrode is to be formed by the use of a half tone mask. Etching is performed with this resist pattern as a mask to form the GB and the pixel electrode. The DB and the channel are formed by one half tone mask and the GB and the pixel electrode are formed by another half tone mask. As a result, the number of exposure processes necessary for fabricating a stagger type TFT substrate can be reduced.

摘要翻译： 一种交错型TFT基板及其制造方法，其中曝光处理次数减少。 在要形成漏极总线（DB）的TFT基板上的区域中形成抗蚀剂图案，并且通过使用半色调掩模在TFT基板上形成TFT。 用该抗蚀剂图案作为掩模进行蚀刻以形成DB和TFT的沟道区域。 此外，在要形成栅极总线（GB）的区域和通过使用半色调掩模形成像素电极的区域中形成抗蚀剂图案。 用该抗蚀剂图案作为掩模进行蚀刻以形成GB和像素电极。 DB和通道由一个半色调掩模形成，并且GB和像素电极由另一个半色调掩模形成。 结果，可以减少制造错开型TFT基板所需的曝光处理次数。

公开(公告)号：US20050170290A1

公开(公告)日：2005-08-04

申请号：US10848610

申请日：2004-05-18

申请人： Yoshio Dejima

发明人： Yoshio Dejima

IPC分类号： G02F1/1368 ,  G02F1/135 ,  G02F1/136 ,  G02F1/1362 ,  G03F7/00 ,  G03F7/20 ,  G09F9/00 ,  H01L21/00 ,  H01L21/027 ,  H01L21/336 ,  H01L21/768 ,  H01L29/786

CPC分类号： G02F1/136227 ,  G02F1/13458 ,  G02F1/136213 ,  G02F2001/136236 ,  G03F1/50

摘要： The invention relates to a method of manufacturing a substrate for a display and a method of manufacturing a display, and it is aimed at providing a display which has high luminance and which can achieve high display quality. A method of manufacturing a substrate for a display is provided in which an insulation film is formed on a gate bus line; a gate bus line terminal is formed on the insulation film; a protective film is formed on the gate bus line terminal; a resist layer formed on the projective film is patterned to form a resist pattern; and the resist pattern is used to form a first contact hole at which the gate bus line is exposed by removing the protective film and the insulation film and to form a second contact hole at which the gate bus line terminal is exposed by removing the protective film, the resist pattern above the second contact hole being formed with a thickness smaller than the thickness of the resist pattern in other regions.

摘要翻译： 本发明涉及制造显示器用基板的方法以及显示器的制造方法，其目的在于提供一种具有高亮度且可实现高显示质量的显示器。 提供一种制造用于显示器的基板的方法，其中在栅极总线上形成绝缘膜; 在绝缘膜上形成栅极总线端子; 在栅极总线端子上形成保护膜; 将形成在投影膜上的抗蚀剂层图案化以形成抗蚀剂图案; 并且抗蚀剂图案用于形成第一接触孔，通过去除保护膜和绝缘膜而露出栅极总线，并形成通过去除保护膜而使栅极总线端子露出的第二接触孔 在第二接触孔上方的抗蚀剂图案形成的厚度小于其它区域中的抗蚀剂图案的厚度。

公开(公告)号：US07259045B2

公开(公告)日：2007-08-21

申请号：US10795787

申请日：2004-03-08

申请人： Yoshio Dejima

发明人： Yoshio Dejima

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/78696

摘要： A stagger type TFT substrate and a fabrication method therefor in which the number of exposure processes is reduced. A resist pattern is formed in an area on the TFT substrate where a drain bus-line (DB) is to be formed and an area on the TFT substrate where a TFT is to be formed by the use of a half tone mask. Etching is performed with this resist pattern as a mask to form the DB and a channel area for the TFT. In addition, a resist pattern is formed in an area where a gate bus-line (GB) is to be formed and an area where a pixel electrode is to be formed by the use of a half tone mask. Etching is performed with this resist pattern as a mask to form the GB and the pixel electrode. The DB and the channel are formed by one half tone mask and the GB and the pixel electrode are formed by another half tone mask. As a result, the number of exposure processes necessary for fabricating a stagger type TFT substrate can be reduced.

摘要翻译： 一种交错型TFT基板及其制造方法，其中曝光处理次数减少。 在要形成漏极总线（DB）的TFT基板上的区域中形成抗蚀剂图案，并且通过使用半色调掩模在TFT基板上形成TFT。 用该抗蚀剂图案作为掩模进行蚀刻以形成DB和TFT的沟道区域。 此外，在要形成栅极总线（GB）的区域和通过使用半色调掩模形成像素电极的区域中形成抗蚀剂图案。 用该抗蚀剂图案作为掩模进行蚀刻以形成GB和像素电极。 DB和通道由一个半色调掩模形成，并且GB和像素电极由另一个半色调掩模形成。 结果，可以减少制造错开型TFT基板所需的曝光处理次数。