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公开(公告)号：US20110188327A1
公开(公告)日：2011-08-04
申请号：US13084026
申请日：2011-04-11
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/065 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C8/16 , G11C29/12
摘要： A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.
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公开(公告)号：US08077530B2
公开(公告)日：2011-12-13
申请号：US13084026
申请日：2011-04-11
CPC分类号： G11C7/12 , G11C7/065 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C8/16 , G11C29/12
摘要： A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.
摘要翻译： 半导体存储器件包括多个存储单元，每个存储单元包括用于保持存储器数据的保持电路，以及一个只读输出电路，用于输出与由保持电路保持的数据相对应的信号。 只读输出电路具有根据由保持电路保持的信号控制的读驱动晶体管。 读取驱动晶体管的栅极长度比包含在保持电路中的晶体管的栅极长度长。 或者，只读输出电路具有根据读取字选择信号控制的读取存取晶体管，并且读取存取晶体管的栅极长度比包含在保持电路中的晶体管的栅极长度长。
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公开(公告)号：US07948787B2
公开(公告)日：2011-05-24
申请号：US12878534
申请日：2010-09-09
CPC分类号： G11C7/12 , G11C7/065 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C8/16 , G11C29/12
摘要： A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.
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公开(公告)号：US07839697B2
公开(公告)日：2010-11-23
申请号：US11961184
申请日：2007-12-20
CPC分类号： G11C7/12 , G11C7/065 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C8/16 , G11C29/12
摘要： A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.
摘要翻译： 半导体存储器件包括多个存储单元，每个存储单元包括用于保持存储器数据的保持电路，以及一个只读输出电路，用于输出与由保持电路保持的数据相对应的信号。 只读输出电路具有根据由保持电路保持的信号控制的读驱动晶体管。 读取驱动晶体管的栅极长度比包含在保持电路中的晶体管的栅极长度长。 或者，只读输出电路具有根据读取字选择信号控制的读取存取晶体管，并且读取存取晶体管的栅极长度比包含在保持电路中的晶体管的栅极长度长。
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公开(公告)号：US20080151653A1
公开(公告)日：2008-06-26
申请号：US11961184
申请日：2007-12-20
CPC分类号： G11C7/12 , G11C7/065 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C8/16 , G11C29/12
摘要： A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.
摘要翻译： 半导体存储器件包括多个存储单元，每个存储单元包括用于保持存储器数据的保持电路，以及一个只读输出电路，用于输出与由保持电路保持的数据相对应的信号。 只读输出电路具有根据由保持电路保持的信号控制的读驱动晶体管。 读取驱动晶体管的栅极长度比包含在保持电路中的晶体管的栅极长度长。 或者，只读输出电路具有根据读取字选择信号控制的读取存取晶体管，并且读取存取晶体管的栅极长度比包含在保持电路中的晶体管的栅极长度长。
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公开(公告)号：US07872893B2
公开(公告)日：2011-01-18
申请号：US11961166
申请日：2007-12-20
IPC分类号： G11C5/06
CPC分类号： G11C11/413
摘要： A semiconductor memory device having a hierarchical bit line structure includes memory cells and an amplification circuit for amplifying a signal read from one of the memory cells via a bit line. A cell N-well region in which the P-channel transistors of the memory cell are formed and an amplification-circuit N-well region in which the P-channel transistors of the amplification circuit are formed are formed continuously.
摘要翻译： 具有分层位线结构的半导体存储器件包括存储单元和用于经由位线放大从一个存储单元读取的信号的放大电路。 连续地形成其中形成有存储单元的P沟道晶体管的单元N阱区域和形成放大电路的P沟道晶体管的放大电路N阱区域。
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公开(公告)号：US20110103126A1
公开(公告)日：2011-05-05
申请号：US13004540
申请日：2011-01-11
IPC分类号： G11C11/419 , G11C5/06 , G11C11/412
CPC分类号： G11C11/418 , G11C8/08
摘要： A control circuit supplies a word line drive voltage to one of m word lines which corresponds to a memory cell to which data is to be written, during a word line drive period including a first period and a second period following the first period, to decrease current capabilities of first and second load transistors included in the memory cell during the first period, and increase the current capabilities of the first and second load transistors during the second period.
摘要翻译： 在包括第一周期和第一周期之后的第二周期的字线驱动周期期间，控制电路将字线驱动电压提供给对应于要写入数据的存储单元的m个字线之一，以减少 在第一周期期间包括在存储单元中的第一和第二负载晶体管的当前能力，并且在第二时段期间增加第一和第二负载晶体管的电流能力。
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公开(公告)号：US08072823B2
公开(公告)日：2011-12-06
申请号：US12910254
申请日：2010-10-22
申请人： Tomoyuki Aihara , Masanori Shirahama , Yoshinobu Yamagami , Marefusa Kurumada , Toshikazu Suzuki
发明人： Tomoyuki Aihara , Masanori Shirahama , Yoshinobu Yamagami , Marefusa Kurumada , Toshikazu Suzuki
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C11/413 , G11C2207/002 , H01L27/0207 , H01L27/1104
摘要： A semiconductor memory device includes a memory cell provided at an intersection of a word line and a bit line, a precharge circuit connected to the bit line, a column select circuit controlled in accordance with a write control signal, and a clamp circuit provided as a write circuit. The clamp circuit includes a transistor configured to control the potential of a selected bit line to a first potential (e.g., 0 V), and a variable capacitor configured to control the potential of the selected bit line to a second potential (e.g., a negative potential) which is lower than the first potential. The capacitance of the variable capacitor decreases when a power supply voltage is increased, whereby the amount of a decrease from the first potential to the second potential is reduced.
摘要翻译： 半导体存储器件包括设置在字线和位线的交叉点处的存储单元，连接到位线的预充电电路，根据写控制信号控制的列选择电路，以及设置为 写电路。 钳位电路包括被配置为将选定位线的电位控制为第一电位（例如，0V）的晶体管，以及被配置为将所选位线的电位控制为第二电位的可变电容（例如，负 电位）低于第一电位。 当电源电压增加时，可变电容器的电容减小，从而第一电位降低到第二电位的量减少。
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公开(公告)号：US08345470B2
公开(公告)日：2013-01-01
申请号：US13004540
申请日：2011-01-11
CPC分类号： G11C11/418 , G11C8/08
摘要： A control circuit supplies a word line drive voltage to one of m word lines which corresponds to a memory cell to which data is to be written, during a word line drive period including a first period and a second period following the first period, to decrease current capabilities of first and second load transistors included in the memory cell during the first period, and increase the current capabilities of the first and second load transistors during the second period.
摘要翻译： 在包括第一周期和第一周期之后的第二周期的字线驱动周期期间，控制电路将字线驱动电压提供给对应于要写入数据的存储单元的m个字线之一，以减少 在第一周期期间包括在存储单元中的第一和第二负载晶体管的当前能力，并且在第二时段期间增加第一和第二负载晶体管的电流能力。
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公开(公告)号：US20060126420A1
公开(公告)日：2006-06-15
申请号：US11338670
申请日：2006-01-25
申请人： Marefusa Kurumada , Yutaka Terada
发明人： Marefusa Kurumada , Yutaka Terada
IPC分类号： G11C8/00
CPC分类号： G11C8/16
摘要： In a multiport memory, in the event of simultaneous read/write operation for the same row address, a read word line pulse signal, output from a read control circuit for memory access based on an externally supplied read enable signal and read clock signal, is input into a write control circuit, to delay start of the write operation until termination of the read operation. This can delay the timing of activating a write word line by a write row decoder behind the timing of activating a read word line by a read row decoder, to allow the read operation first followed by the write operation. Therefore, since the read operation is performed while the write word line being kept closed, the trouble of data processing becoming uncertain due to addition of the load of a write bit line to a read bit line can be prevented.
摘要翻译： 在多端口存储器中，在对同一行地址进行同时读/写操作的情况下，基于外部提供的读使能信号和读时钟信号从用于存储器访问的读控制电路输出的读字字脉冲信号是 输入到写入控制电路中，以延迟写入操作的开始直到读取操作结束。 这可以通过读行解码器在激活读字线的定时之后延迟由写行解码器激活写字线的定时，以允许读操作首先跟随写操作。 因此，由于在写入字线保持关闭的同时执行读取操作，因此可以防止由于将写入位线的负载加到读取位线而使数据处理变得不确定的问题。
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