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公开(公告)号：US20110188327A1
公开(公告)日：2011-08-04
申请号：US13084026
申请日：2011-04-11
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/065 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C8/16 , G11C29/12
摘要： A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.
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公开(公告)号：US08077530B2
公开(公告)日：2011-12-13
申请号：US13084026
申请日：2011-04-11
CPC分类号： G11C7/12 , G11C7/065 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C8/16 , G11C29/12
摘要： A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.
摘要翻译： 半导体存储器件包括多个存储单元，每个存储单元包括用于保持存储器数据的保持电路，以及一个只读输出电路，用于输出与由保持电路保持的数据相对应的信号。 只读输出电路具有根据由保持电路保持的信号控制的读驱动晶体管。 读取驱动晶体管的栅极长度比包含在保持电路中的晶体管的栅极长度长。 或者，只读输出电路具有根据读取字选择信号控制的读取存取晶体管，并且读取存取晶体管的栅极长度比包含在保持电路中的晶体管的栅极长度长。
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公开(公告)号：US07948787B2
公开(公告)日：2011-05-24
申请号：US12878534
申请日：2010-09-09
CPC分类号： G11C7/12 , G11C7/065 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C8/16 , G11C29/12
摘要： A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.
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公开(公告)号：US07839697B2
公开(公告)日：2010-11-23
申请号：US11961184
申请日：2007-12-20
CPC分类号： G11C7/12 , G11C7/065 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C8/16 , G11C29/12
摘要： A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.
摘要翻译： 半导体存储器件包括多个存储单元，每个存储单元包括用于保持存储器数据的保持电路，以及一个只读输出电路，用于输出与由保持电路保持的数据相对应的信号。 只读输出电路具有根据由保持电路保持的信号控制的读驱动晶体管。 读取驱动晶体管的栅极长度比包含在保持电路中的晶体管的栅极长度长。 或者，只读输出电路具有根据读取字选择信号控制的读取存取晶体管，并且读取存取晶体管的栅极长度比包含在保持电路中的晶体管的栅极长度长。
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公开(公告)号：US20080151653A1
公开(公告)日：2008-06-26
申请号：US11961184
申请日：2007-12-20
CPC分类号： G11C7/12 , G11C7/065 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C8/16 , G11C29/12
摘要： A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.
摘要翻译： 半导体存储器件包括多个存储单元，每个存储单元包括用于保持存储器数据的保持电路，以及一个只读输出电路，用于输出与由保持电路保持的数据相对应的信号。 只读输出电路具有根据由保持电路保持的信号控制的读驱动晶体管。 读取驱动晶体管的栅极长度比包含在保持电路中的晶体管的栅极长度长。 或者，只读输出电路具有根据读取字选择信号控制的读取存取晶体管，并且读取存取晶体管的栅极长度比包含在保持电路中的晶体管的栅极长度长。
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6.发明申请COMPOSITION FOR FORMING A RESIST UNDERLAYER FILM INCLUDING HYDROXYL GROUP-CONTAINING CARBAZOLE NOVOLAC RESIN 有权用于形成耐下层膜的组合物，包括含有羟基的含羧基芳香酚醛树脂公开(公告)号：US20130280913A1
公开(公告)日：2013-10-24
申请号：US13992864
申请日：2011-12-05
申请人： Tetsuya Shinjo , Hiroaki Okuyama , Keisuke Hashimoto , Yasunobu Someya , Ryo Karasawa , Masakazu Kato
发明人： Tetsuya Shinjo , Hiroaki Okuyama , Keisuke Hashimoto , Yasunobu Someya , Ryo Karasawa , Masakazu Kato
IPC分类号： H01L21/308 , H01L21/027 , C09D139/04
CPC分类号： H01L21/3081 , C09D139/04 , G03F7/0045 , G03F7/091 , G03F7/094 , H01L21/0271
摘要： There is provided a composition for forming a resist underlayer film having heat resistance for use in a lithography process in semiconductor device production. A composition for forming a resist underlayer film, comprising a polymer that contains a unit structure of formula (1) and a unit structure of formula (2) in a proportion of 3 to 97:97 to 3 in molar ratio: A method for producing a semiconductor device, including the steps of: forming an underlayer film using the composition for forming a resist underlayer film on a semiconductor substrate; forming a hard mask on the underlayer film; further forming a resist film on the hard mask; forming a patterned resist film and developing; etching the hard mask according to the patterned resist film; etching the underlayer film according to the patterned hard mask; and processing the semiconductor substrate according to the patterned underlayer film.
摘要翻译： 提供了一种用于形成半导体器件制造中用于光刻工艺的具有耐热性的抗蚀剂下层膜的组合物。 一种形成抗蚀剂下层膜的组合物，其含有以式（1）的单元结构的聚合物和式（2）的单元结构，其比例为3至97:97至3的摩尔比。 半导体器件，包括以下步骤：使用在半导体衬底上形成抗蚀剂下层膜的组合物形成下层膜; 在下层膜上形成硬掩模; 进一步在硬掩模上形成抗蚀剂膜; 形成图案化的抗蚀剂膜并显影; 根据图案化的抗蚀剂膜蚀刻硬掩模; 根据图案化的硬掩模蚀刻下层膜; 以及根据图案化的下层膜处理半导体衬底。
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公开(公告)号：US20080094870A1
公开(公告)日：2008-04-24
申请号：US11976239
申请日：2007-10-23
申请人： Kazuki Tsujimura , Hiroaki Okuyama
发明人： Kazuki Tsujimura , Hiroaki Okuyama
CPC分类号： H01L27/1104 , G11C5/063 , G11C11/412 , H01L27/11
摘要： A semiconductor memory device includes a memory cell array and peripheral control circuits. In each of the peripheral control circuits, a plurality of transistors are arranged at a substantially constant transistor pitch in a first direction which is the row direction or the column direction of the memory cell array. In the memory cell array, a memory cell length in the first direction is substantially n times the transistor pitch, wherein n is an integer.
摘要翻译： 半导体存储器件包括存储单元阵列和外围控制电路。 在每个外围控制电路中，在作为存储单元阵列的行方向或列方向的第一方向上以大致恒定的晶体管间隔布置多个晶体管。 在存储单元阵列中，第一方向上的存储单元长度基本上是晶体管间距的n倍，其中n是整数。
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公开(公告)号：US4947379A
公开(公告)日：1990-08-07
申请号：US207650
申请日：1988-06-16
申请人： Hiroaki Okuyama
发明人： Hiroaki Okuyama
IPC分类号： G11C11/41 , G11C8/18 , G11C11/416 , G11C11/419
CPC分类号： G11C11/416 , G11C11/419 , G11C8/18
摘要： A static random access memory (RAM) circuit arranged such that the data stored in a memory cell is readout by detecting a transition address signal level. That is, an address transition pulse is generated by detecting an address signal transition, and first and second pulses are generated by detecting a starting edge and a trailing edge of the address transition pulse respectively. The first pulse enables a selected word line for reading out the data stored in selected memory cells. The second pulse enables an data output circuit coupled to the bit lines for transferring the readout data to an output terminal. Under such an arrangement, memory access operation becomes faster, and even if "skew" phenomenon is caused, the transient data readout from the memory cells instantaneously is prevented from being transferred to the output terminal.
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9.发明授权Semiconductor storage device with block writing function and reduce power consumption thereof 失效具有块写功能的半导体存储器件，并降低功耗公开(公告)号：US06304943B1
公开(公告)日：2001-10-16
申请号：US09090983
申请日：1998-06-05
申请人： Hiroaki Okuyama
发明人： Hiroaki Okuyama
IPC分类号： G06F1200
CPC分类号： G11C11/419 , G06F12/0804 , Y02D10/13
摘要： In a system using a microprocessor including a cache memory, a specific memory cell row including at least one row of memory cells is provided to a cache memory cell array of the cache memory so as to be used as a write back buffer. When data is to be saved in the specific memory cell row (write back buffer), the memory cells aligned in one row in the cache memory cell array are selected by an arbitrary word line, and all the data to be saved are simultaneously written in the specific memory cell row (write back buffer) through bit line pairs in a batch. Therefore, since the data to be saved can be written in the specific memory cell row (write back buffer) without using a data bus, the number of accesses to be made to the cache memory can be decreased. As a result, the throughput can be improved and the power consumption of the microprocessor can be decreased. In addition, since the write back buffer is constituted by the specific memory cell row, the chip area can be decreased.
摘要翻译： 在使用包括高速缓存存储器的微处理器的系统中，将包括至少一行存储器单元的特定存储单元行提供给高速缓冲存储器的高速缓冲存储器单元阵列，以用作回写缓冲器。 当将数据保存在特定存储单元行（写回缓冲器）中时，通过任意字线选择在高速缓存存储单元阵列中的一行中对齐的存储单元，并将所有待保存的数据同时写入 特定的存储单元行（回写缓冲区）通过位线对进行批处理。 因此，由于可以在不使用数据总线的情况下将要保存的数据写入特定存储单元行（回写缓冲器），所以可以减少对高速缓冲存储器的访问次数。 结果，可以提高吞吐量并且可以降低微处理器的功耗。 此外，由于回写缓冲器由特定存储单元行构成，因此可以减小芯片面积。
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公开(公告)号：US4893276A
公开(公告)日：1990-01-09
申请号：US277195
申请日：1988-11-29
申请人： Hiroaki Okuyama
发明人： Hiroaki Okuyama
IPC分类号： G11C11/417 , G11C7/10 , G11C11/409 , G11C11/419 , H01L27/10 , H03K19/0175
CPC分类号： G11C7/1057 , G11C11/419 , G11C7/1051
摘要： An output circuit of a static random access memory is designed to set the output voltage of the data output circuit to an intermediate voltage by detecting the transition of the address signal before the data in a memory cell is read out from the memory cell, and then, the output voltage of the data output circuit is changed from the intermediate voltage to an H level or from the intermediate voltage to an L level. In this way, since the output voltage changes from the intermediate voltage to an H level or an L level, the transition time of the output voltage is shortened, and therefore the speed of a data reading operation may be increased. At the same time, the momentary current through the data output circuit may be decreased.
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