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公开(公告)号：US20110188327A1
公开(公告)日：2011-08-04
申请号：US13084026
申请日：2011-04-11
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/065 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C8/16 , G11C29/12
摘要： A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.
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公开(公告)号：US08077530B2
公开(公告)日：2011-12-13
申请号：US13084026
申请日：2011-04-11
CPC分类号： G11C7/12 , G11C7/065 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C8/16 , G11C29/12
摘要： A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.
摘要翻译： 半导体存储器件包括多个存储单元，每个存储单元包括用于保持存储器数据的保持电路，以及一个只读输出电路，用于输出与由保持电路保持的数据相对应的信号。 只读输出电路具有根据由保持电路保持的信号控制的读驱动晶体管。 读取驱动晶体管的栅极长度比包含在保持电路中的晶体管的栅极长度长。 或者，只读输出电路具有根据读取字选择信号控制的读取存取晶体管，并且读取存取晶体管的栅极长度比包含在保持电路中的晶体管的栅极长度长。
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公开(公告)号：US20080151653A1
公开(公告)日：2008-06-26
申请号：US11961184
申请日：2007-12-20
CPC分类号： G11C7/12 , G11C7/065 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C8/16 , G11C29/12
摘要： A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.
摘要翻译： 半导体存储器件包括多个存储单元，每个存储单元包括用于保持存储器数据的保持电路，以及一个只读输出电路，用于输出与由保持电路保持的数据相对应的信号。 只读输出电路具有根据由保持电路保持的信号控制的读驱动晶体管。 读取驱动晶体管的栅极长度比包含在保持电路中的晶体管的栅极长度长。 或者，只读输出电路具有根据读取字选择信号控制的读取存取晶体管，并且读取存取晶体管的栅极长度比包含在保持电路中的晶体管的栅极长度长。
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公开(公告)号：US07948787B2
公开(公告)日：2011-05-24
申请号：US12878534
申请日：2010-09-09
CPC分类号： G11C7/12 , G11C7/065 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C8/16 , G11C29/12
摘要： A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.
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公开(公告)号：US07839697B2
公开(公告)日：2010-11-23
申请号：US11961184
申请日：2007-12-20
CPC分类号： G11C7/12 , G11C7/065 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C8/16 , G11C29/12
摘要： A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.
摘要翻译： 半导体存储器件包括多个存储单元，每个存储单元包括用于保持存储器数据的保持电路，以及一个只读输出电路，用于输出与由保持电路保持的数据相对应的信号。 只读输出电路具有根据由保持电路保持的信号控制的读驱动晶体管。 读取驱动晶体管的栅极长度比包含在保持电路中的晶体管的栅极长度长。 或者，只读输出电路具有根据读取字选择信号控制的读取存取晶体管，并且读取存取晶体管的栅极长度比包含在保持电路中的晶体管的栅极长度长。
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公开(公告)号：US07872893B2
公开(公告)日：2011-01-18
申请号：US11961166
申请日：2007-12-20
IPC分类号： G11C5/06
CPC分类号： G11C11/413
摘要： A semiconductor memory device having a hierarchical bit line structure includes memory cells and an amplification circuit for amplifying a signal read from one of the memory cells via a bit line. A cell N-well region in which the P-channel transistors of the memory cell are formed and an amplification-circuit N-well region in which the P-channel transistors of the amplification circuit are formed are formed continuously.
摘要翻译： 具有分层位线结构的半导体存储器件包括存储单元和用于经由位线放大从一个存储单元读取的信号的放大电路。 连续地形成其中形成有存储单元的P沟道晶体管的单元N阱区域和形成放大电路的P沟道晶体管的放大电路N阱区域。
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公开(公告)号：US20080151606A1
公开(公告)日：2008-06-26
申请号：US11961166
申请日：2007-12-20
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： A semiconductor memory device having a hierarchical bit line structure includes memory cells and an amplification circuit for amplifying a signal read from one of the memory cells via a bit line. A cell N-well region in which the P-channel transistors of the memory cell are formed and an amplification-circuit N-well region in which the P-channel transistors of the amplification circuit are formed are formed continuously.
摘要翻译： 具有分层位线结构的半导体存储器件包括存储单元和用于经由位线放大从一个存储单元读取的信号的放大电路。 连续地形成其中形成有存储单元的P沟道晶体管的单元N阱区域和形成放大电路的P沟道晶体管的放大电路N阱区域。
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公开(公告)号：US07692955B2
公开(公告)日：2010-04-06
申请号：US12039585
申请日：2008-02-28
IPC分类号： G11C11/00
摘要： A semiconductor integrated circuit includes: a memory cell array including a plurality of SRAM memory cells; a characteristic measuring circuit including a plurality of transistor circuits connected in parallel; and a first terminal. The plurality of transistor circuits each include a first transistor configured in the same manner as one of transistors included in one of the SRAM memory cells. The first transistor is connected so as to control current between the first terminal and a node at a reference potential according to a voltage supplied to a gate of the first transistor.
摘要翻译： 半导体集成电路包括：包括多个SRAM存储单元的存储单元阵列; 包括并联连接的多个晶体管电路的特性测量电路; 和第一个终端。 多个晶体管电路各自包括以与包括在SRAM存储单元之一中的晶体管中的一个相同的方式配置的第一晶体管。 第一晶体管被连接以便根据提供给第一晶体管的栅极的电压来控制第一端子和参考电位的节点之间的电流。
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公开(公告)号：US20080253171A1
公开(公告)日：2008-10-16
申请号：US12039585
申请日：2008-02-28
IPC分类号： G11C11/00
摘要： A semiconductor integrated circuit includes: a memory cell array including a plurality of SRAM memory cells; a characteristic measuring circuit including a plurality of transistor circuits connected in parallel; and a first terminal. The plurality of transistor circuits each include a first transistor configured in the same manner as one of transistors included in one of the SRAM memory cells. The first transistor is connected so as to control current between the first terminal and a node at a reference potential according to a voltage supplied to a gate of the first transistor.
摘要翻译： 半导体集成电路包括：包括多个SRAM存储单元的存储单元阵列; 包括并联连接的多个晶体管电路的特性测量电路; 和第一个终端。 多个晶体管电路各自包括以与包括在SRAM存储单元之一中的晶体管中的一个相同的方式配置的第一晶体管。 第一晶体管被连接以便根据提供给第一晶体管的栅极的电压来控制第一端子和参考电位的节点之间的电流。
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公开(公告)号：US08345470B2
公开(公告)日：2013-01-01
申请号：US13004540
申请日：2011-01-11
CPC分类号： G11C11/418 , G11C8/08
摘要： A control circuit supplies a word line drive voltage to one of m word lines which corresponds to a memory cell to which data is to be written, during a word line drive period including a first period and a second period following the first period, to decrease current capabilities of first and second load transistors included in the memory cell during the first period, and increase the current capabilities of the first and second load transistors during the second period.
摘要翻译： 在包括第一周期和第一周期之后的第二周期的字线驱动周期期间，控制电路将字线驱动电压提供给对应于要写入数据的存储单元的m个字线之一，以减少 在第一周期期间包括在存储单元中的第一和第二负载晶体管的当前能力，并且在第二时段期间增加第一和第二负载晶体管的电流能力。
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