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公开(公告)号：US08089565B2
公开(公告)日：2012-01-03
申请号：US11579596
申请日：2004-12-15
IPC分类号： H04N5/63
CPC分类号： G09G5/006 , H04N5/06 , H04N5/4401 , H04N5/602 , H04N21/4341 , H04N21/4436
摘要： A digital signal receiver comprises a signal separating section (11), a clock signal generating section (12), a video data processing section (14), an audio data processing section (15), and a control section (17). The clock signal generating section (12) generates an operation clock signal (105) for the signal separating section (11), the video data processing section (14), and the audio data processing section (15). The control section (17) pauses the signal separating section (11), the video data processing section (14), and the audio data processing section (15) until receiving a clock stability signal (108) indicating that the operation clock signal (105) is stable, the clock stability signal (108) being generated by the clock signal generating section (12).
摘要翻译： 数字信号接收机包括信号分离部分（11），时钟信号产生部分（12），视频数据处理部分（14），音频数据处理部分（15）和控制部分（17）。 时钟信号生成部（12）生成信号分离部（11），视频数据处理部（14）和音频数据处理部（15）的操作时钟信号（105）。 控制部分（17）暂停信号分离部分（11），视频数据处理部分（14）和音频数据处理部分（15），直到接收到指示操作时钟信号（105）的时钟稳定信号 ）稳定，时钟稳定信号（108）由时钟信号产生部分（12）产生。
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公开(公告)号：US20080136970A1
公开(公告)日：2008-06-12
申请号：US11579596
申请日：2004-12-15
IPC分类号： H04N5/455
CPC分类号： G09G5/006 , H04N5/06 , H04N5/4401 , H04N5/602 , H04N21/4341 , H04N21/4436
摘要： A digital signal receiver comprises a signal separating section (11), a clock signal generating section (12), a video data processing section (14), an audio data processing section (15), and a control section (17). The clock signal generating section (12) generates an operation clock signal (105) for the signal separating section (11), the video data processing section (14), and the audio data processing section (15). The control section (17) pauses the signal separating section (11), the video data processing section (14), and the audio data processing section (15) until receiving a clock stability signal (108) indicating that the operation clock signal (105) is stable, the clock stability signal (108) being generated by the clock signal generating section (12).
摘要翻译： 数字信号接收机包括信号分离部分（11），时钟信号产生部分（12），视频数据处理部分（14），音频数据处理部分（15）和控制部分（17）。 时钟信号生成部（12）生成信号分离部（11），视频数据处理部（14）和音频数据处理部（15）的操作时钟信号（105）。 控制部分（17）暂停信号分离部分（11），视频数据处理部分（14）和音频数据处理部分（15），直到接收到指示操作时钟信号（105）的时钟稳定信号 ）稳定，时钟稳定信号（108）由时钟信号产生部分（12）产生。
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3.发明申请Video signal processor, method using the same, display device and method using the same 有权视频信号处理器，使用该方法的方法，显示装置和使用其的方法公开(公告)号：US20050231493A1
公开(公告)日：2005-10-20
申请号：US11071190
申请日：2005-03-04
申请人： Satoshi Takahashi , Ryogo Yanagisawa , Toru Iwata
发明人： Satoshi Takahashi , Ryogo Yanagisawa , Toru Iwata
CPC分类号： G09G5/006 , G09G3/2092
摘要： A video signal processor for processing input video data in accordance with an input clock signal includes: an input section for changing the format of the video data and outputting resultant data; a logic section for decoding the data output from the input section and outputting decoded data; and a frequency detector for detecting that the clock signal has a frequency higher than a given frequency and outputting a result of the detection as a detection signal. When the frequency of the clock signal is higher than the given frequency, operation of at least part of circuits constituting the video signal processor is stopped in accordance with the detection signal.
摘要翻译： 用于根据输入时钟信号处理输入视频数据的视频信号处理器包括：输入部分，用于改变视频数据的格式并输出结果数据; 逻辑部分，用于对从输入部分输出的数据进行解码并输出解码数据; 以及频率检测器，用于检测时钟信号具有高于给定频率的频率，并将检测结果作为检测信号输出。 当时钟信号的频率高于给定频率时，根据检测信号停止构成视频信号处理器的电路的至少一部分的操作。
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公开(公告)号：US20050104876A1
公开(公告)日：2005-05-19
申请号：US11020046
申请日：2004-12-23
摘要： In a transmitting section for a video signal transmitting/receiving system for transmitting digital video signals using a plurality of transmission channels, video guard band signals are inserted into video signals associated with the transmission channels immediately before transition from a blanking region to an effective video region. In a receiving section for the system, the inserted video guard band signals are detected for the respective transmission channels. A skew among the transmission channels is detected based on the detection result. To synchronize the video guard band signals among all the transmission channels, with reference to one of the video signals associated with a transmission channel with the longest delay (i.e., delayed by one clock cycle 1T), a delay of 1T is given to the other video signals. As a result, even if a skew occurs among the transmission channels, correct pixel data is displayed.
摘要翻译： 在用于使用多个发送信道发送数字视频信号的视频信号发送/接收系统的发送部分中，在从消隐区域到有效视频区域的转换之前，将视频保护带信号插入到与传输信道相关联的视频信号中 。 在系统的接收部分中，针对各个传输信道检测插入的视频保护频带信号。 基于检测结果检测传输信道之间的偏移。 为了使所有传输信道中的视频保护频带信号同步，参考与具有最长延迟（即，延迟一个时钟周期1T）的传输信道相关联的视频信号之一，将1T的延迟给予 其他视频信号。 结果，即使在发送信道之间发生偏斜，也显示正确的像素数据。
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5.发明授权Video signal processor capable of suppressing excessive heat generation, method using the same, display device and method using the same 有权能够抑制过度发热的视频信号处理器，使用其的方法，显示装置及使用其的方法公开(公告)号：US07864252B2
公开(公告)日：2011-01-04
申请号：US11071190
申请日：2005-03-04
申请人： Satoshi Takahashi , Ryogo Yanagisawa , Toru Iwata
发明人： Satoshi Takahashi , Ryogo Yanagisawa , Toru Iwata
CPC分类号： G09G5/006 , G09G3/2092
摘要： A video signal processor for processing input video data in accordance with an input clock signal includes: an input section for changing the format of the video data and outputting resultant data; a logic section for decoding the data output from the input section and outputting decoded data; and a frequency detector for detecting that the clock signal has a frequency higher than a given frequency and outputting a result of the detection as a detection signal. When the frequency of the clock signal is higher than the given frequency, operation of at least part of circuits constituting the video signal processor is stopped in accordance with the detection signal.
摘要翻译： 用于根据输入时钟信号处理输入视频数据的视频信号处理器包括：输入部分，用于改变视频数据的格式并输出结果数据; 逻辑部分，用于对从输入部分输出的数据进行解码并输出解码数据; 以及频率检测器，用于检测时钟信号具有高于给定频率的频率，并将检测结果作为检测信号输出。 当时钟信号的频率高于给定频率时，根据检测信号停止构成视频信号处理器的电路的至少一部分的操作。
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公开(公告)号：US07321403B2
公开(公告)日：2008-01-22
申请号：US11020046
申请日：2004-12-23
摘要： In a transmitting section for a video signal transmitting/receiving system for transmitting digital video signals using a plurality of transmission channels, video guard band signals are inserted into video signals associated with the transmission channels immediately before transition from a blanking region to an effective video region. In a receiving section for the system, the inserted video guard band signals are detected for the respective transmission channels. A skew among the transmission channels is detected based on the detection result. To synchronize the video guard band signals among all the transmission channels, with reference to one of the video signals associated with a transmission channel with the longest delay (i.e., delayed by one clock cycle 1T), a delay of 1T is given to the other video signals. As a result, even if a skew occurs among the transmission channels, correct pixel data is displayed.
摘要翻译： 在用于使用多个发送信道发送数字视频信号的视频信号发送/接收系统的发送部分中，在从消隐区域到有效视频区域的转换之前，将视频保护带信号插入到与传输信道相关联的视频信号中 。 在系统的接收部分中，针对各个传输信道检测插入的视频保护频带信号。 基于检测结果检测传输信道之间的偏移。 为了使所有传输信道中的视频保护频带信号同步，参考与具有最长延迟（即，延迟一个时钟周期1T）的传输信道相关联的视频信号之一，将1T的延迟给予 其他视频信号。 结果，即使在发送信道之间发生偏斜，也显示正确的像素数据。
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公开(公告)号：US20090028280A1
公开(公告)日：2009-01-29
申请号：US12280726
申请日：2007-01-09
IPC分类号： H04L7/00
CPC分类号： H04L7/0008 , G09G5/008 , G09G2370/12 , H04N21/242 , H04N21/4302
摘要： A clock control circuit 22 in a control circuit 21 provided in a transmitter 25 controls a gate circuit 12 based on an instruction from a microcomputer 32 to stop the output of the clock to a cable 115 for a first predetermined period of time. Then, a read-out circuit in the microcomputer 32 accesses an EDID 31 stored in an information storing circuit of a receiver 43 via the cable 115, and specifies the first predetermined period of time based on the EDID 31. A reconfiguration circuit 42 provided in the receiver 43 counts the clock-holding state, and resets at least one of the receiver 43 and a TV 114 if the clock has been stopped for a second predetermined period of time. This reset operation suppresses the display of noise on the TV 114. Therefore, the occurrence of noise due to mis-latching between the clock and the data can be reduced even after a signal switching that entails a change in the clock frequency.
摘要翻译： 设置在发送器25中的控制电路21中的时钟控制电路22基于来自微型计算机32的指令来控制门电路12，以在第一预定时间段内将时钟的输出停止到电缆115。 然后，微计算机32中的读出电路通过电缆115访问存储在接收机43的信息存储电路中的EDID 31，并基于EDID 31指定第一预定时间段。一种重配置电路42， 接收器43计数时钟保持状态，并且如果时钟已经停止了第二预定时间段，则复位接收器43和TV 114中的至少一个。 该复位操作抑制TV 114上的噪声的显示。因此，即使在需要时钟频率变化的信号切换之后，也可以减少由于时钟和数据之间的误锁而引起的噪声的发生。
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公开(公告)号：US20090257453A1
公开(公告)日：2009-10-15
申请号：US12420506
申请日：2009-04-08
申请人： Ryogo Yanagisawa , Syuji Kato , Satoshi Takahashi
发明人： Ryogo Yanagisawa , Syuji Kato , Satoshi Takahashi
IPC分类号： H04J1/00
CPC分类号： H04N7/083 , G09G5/008 , G09G2370/12 , H03L7/093 , H03L7/18 , H04L7/0008
摘要： In an audio and video transmission apparatus, a frequency division parameter control unit outputs a frequency division parameter Pt, Qt for relating a pixel clock (frequency: pclk) for video data with an audio clock (frequency: ft) for audio data. An audio/video/packet multiplexing unit converts audio data and the frequency division parameter Pt, Qt into packets, and superimposes the packets into blanking intervals of video data, thereby producing transmission data. The frequency division parameter Pt, Qt satisfies a relationship represented by: pclk/Pt=ft/Qt=fpt, and cause fpt to have a value that falls outside of a predetermined band that is determined as the band of audio data.
摘要翻译： 在音频和视频传输装置中，分频参数控制单元输出用于将视频数据的像素时钟（频率：pclk）与用于音频数据的音频时钟（频率：ft）相关联的分频参数Pt，Qt。 音频/视频/分组复用单元将音频数据和分频参数Pt，Qt转换为分组，并将分组叠加到视频数据的消隐间隔中，从而产生传输数据。 分频参数Pt，Qt满足由pclk / Pt = ft / Qt = fpt表示的关系，并且使得fpt具有落在被确定为音频数据的频带的预定频带之外的值。
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公开(公告)号：US20090052599A1
公开(公告)日：2009-02-26
申请号：US12279765
申请日：2006-11-30
IPC分类号： H04L7/00
CPC分类号： H04L7/0083 , G09G5/008 , G09G2320/0238 , H03L7/16 , H03M9/00 , H04N21/4122 , H04N21/43632
摘要： The present invention provides a transmitter capable of reducing the occurrence of noise when switching from the SD signal to the HD signal, for example. A microcomputer (151) controls a 10-times multiplication PLL (13) to increase the amount of jitter of a multiplied clock (CLK1×10) upon signal switching, i.e., when switching the frequency of an input clock (CLK1) from one to another. Alternatively, it controls a phase adjustment section (31) to increase the amount of jitter of a transmit clock (CLK2). Alternatively, it controls a fixed data producing section (61) to set transmit data (DATA2) to predetermined fixed data stored in a fixed data storing section (62).
摘要翻译： 本发明提供了一种例如在从SD信号切换到HD信号时能够减少噪声的发生的发送机。 微控制器（151）控制10倍乘法PLL（13），以便在信号切换时，即当将输入时钟（CLK1）的频率从一个切换到另一个时，增加倍增时钟（CLK1×10）的抖动量。 或者，它控制相位调整部分（31）以增加发送时钟（CLK2）的抖动量。 或者，它控制固定数据产生部分（61）将发送数据（DATA2）设置为存储在固定数据存储部分（62）中的预定固定数据。
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公开(公告)号：US20070005163A1
公开(公告)日：2007-01-04
申请号：US11407084
申请日：2006-04-20
申请人： Satoshi Takahashi , Shuji Kato
发明人： Satoshi Takahashi , Shuji Kato
IPC分类号： G06F17/00
CPC分类号： H04S7/00
摘要： An audio information detector extracts frequency information on audio data from a packet called an ASP in the HDMI standard and outputs the extracted frequency information to a frequency divider as audio information. The frequency divider determines a frequency division ratio based on the audio information, divides the frequency of a PLL clock signal output from an analog PLL circuit by the frequency division ratio and outputs the resultant signal as a comparison clock signal. The analog PLL circuit performs feedback control such that the comparison clock signal and a reference clock signal are synchronized with each other, and generates an audio clock signal obtained by performing frequency multiplication or division on the reference clock signal.
摘要翻译： 音频信息检测器从HDMI标准中的称为ASP的分组中提取关于音频数据的频率信息，并将所提取的频率信息作为音频信息输出到分频器。 分频器基于音频信息确定分频比，将从模拟PLL电路输出的PLL时钟信号的频率除以分频比，并将所得到的信号作为比较时钟信号输出。 模拟PLL电路执行反馈控制，使得比较时钟信号和参考时钟信号彼此同步，并且产生通过对参考时钟信号执行倍频或除法而获得的音频时钟信号。
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