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12 条记录 (耗时 0.017 秒)

    Barrier layer fabrication methods
    1.
    发明授权
    Barrier layer fabrication methods 有权
    阻隔层制造方法

    公开(公告)号：US06426306B1

    公开(公告)日：2002-07-30

    申请号：US09713845

    申请日：2000-11-15

    申请人： Scott J. Deboer ,  Randhir P. S. Thakur

    发明人： Scott J. Deboer ,  Randhir P. S. Thakur

    IPC分类号： H01L2131

    CPC分类号： H01L28/75 ,  H01L21/28568 ,  H01L27/1085 ,  H01L28/55 ,  H01L28/60

    摘要： A process for forming a storage capacitor for a semiconductor assembly, by forming a first storage electrode having a top surface consisting of titanium nitride; forming a barrier layer directly on the titanium nitride, the barrier layer (a material containing any one of amorphous silicon, tantalum, titanium, or strontium) being of sufficient thickness to substantially limit the oxidation of the titanium nitride when the semiconductor assembly is subjected to an oxidizing agent (either an oxidizing agent or an nitridizing agent); converting a portion of the barrier layer to a dielectric compound; depositing a storage cell dielectric directly on the dielectric compound, the storage cell dielectric being of the same chemical makeup as the dielectric compound and thereby using the dielectric compound as a nucleation surface; and forming a second capacitor electrode on the storage cell dielectric.

    摘要翻译： 一种用于形成半导体组件的存储电容器的方法，其特征在于，形成具有由氮化钛组成的顶表面的第一存储电极; 在氮化钛上直接形成阻挡层，阻挡层（含有非晶硅，钽，钛或锶中的任何一种的材料）具有足够的厚度，以在半导体组件经受时基本上限制氮化钛的氧化 氧化剂（氧化剂或氮化剂）; 将阻挡层的一部分转变为电介质化合物; 将存储单元电介质直接沉积在电介质化合物上，储能单元电介质具有与电介质化合物相同的化学组成，从而使用电介质化合物作为成核面; 以及在所述存储单元电介质上形成第二电容器电极。

    Barrier layer fabrication methods
    2.
    发明授权
    Barrier layer fabrication methods 失效
    阻隔层制造方法

    公开(公告)号：US06180481B2

    公开(公告)日：2001-01-30

    申请号：US09004932

    申请日：1998-01-09

    申请人： Scott J. Deboer ,  Randhir P. S. Thakur

    发明人： Scott J. Deboer ,  Randhir P. S. Thakur

    IPC分类号： H01L218242

    CPC分类号： H01L28/75 ,  H01L21/28568 ,  H01L27/1085 ,  H01L28/55 ,  H01L28/60

    摘要： Exemplary embodiments of the present invention teach a process for forming a storage capacitor for a semiconductor assembly, by forming a first storage electrode having a top surface consisting of titanium nitride; forming a barrier layer directly on the titanium nitride, the barrier layer (a material containing any one of amorphous silicon, tantalum, titanium, or strontium) being of sufficient thickness to substantially limit the oxidation of the titanium nitride when said semiconductor assembly is subjected to an oxidizing agent (either an oxidizing agent or an nitridizing agent); converting a portion of the barrier layer to a dielectric compound; depositing a storage cell dielectric directly on the dielectric compound, the storage cell dielectric being of the same chemical makeup as the dielectric compound and thereby using the dielectric compound as a nucleation surface; and forming a second capacitor electrode on the storage cell dielectric.

    摘要翻译： 本发明的示例性实施例通过形成具有由氮化钛组成的顶表面的第一存储电极来教导形成用于半导体组件的存储电容器的工艺; 在氮化钛上直接形成阻挡层，阻挡层（含有非晶硅，钽，钛或锶中的任何一种的材料）具有足够的厚度，以在所述半导体组件经受时基本上限制氮化钛的氧化 氧化剂（氧化剂或氮化剂）; 将阻挡层的一部分转变为电介质化合物; 将存储单元电介质直接沉积在电介质化合物上，储能单元电介质具有与电介质化合物相同的化学组成，从而使用电介质化合物作为成核面; 以及在所述存储单元电介质上形成第二电容器电极。

    DRAM capacitors made from silicon-germanium and electrode-limited conduction dielectric films
    3.
    发明授权
    DRAM capacitors made from silicon-germanium and electrode-limited conduction dielectric films 失效
    由硅锗制成的DRAM电容器和电极限制导电介电膜

    公开(公告)号：US6150208A

    公开(公告)日：2000-11-21

    申请号：US76333

    申请日：1998-05-11

    申请人： Scott J. Deboer ,  Klaus F. Schuegraf ,  Ronald A. Weimer ,  Randhir P. S. Thakur

    发明人： Scott J. Deboer ,  Klaus F. Schuegraf ,  Ronald A. Weimer ,  Randhir P. S. Thakur

    IPC分类号： H01L21/02 ,  H01L21/8242

    CPC分类号： H01L28/40 ,  H01L27/10852

    摘要： An exemplary implementation of the present invention includes a capacitor for a dynamic random access memory cell having a first plate; a second plate; and a dielectric layer interposed between said first and second plates, with the dielectric layer being dominated by electrode-limited conduction, which includes tantalum pentoxide and silicon nitride, or a combination of the two. In a preferred implementation, one of the two capacitor plates is formed from a silicon-germanium layer, the second plate is formed from a metal and the dielectric layer is formed from tantalum pentoxide.

    摘要翻译： 本发明的示例性实施例包括一种用于具有第一板的动态随机存取存储单元的电容器; 第二盘 以及插入在所述第一和第二板之间的电介质层，其中所述电介质层由电极限制导电支配，其包括五氧化二钽和氮化硅，或两者的组合。 在优选的实施方式中，两个电容器板之一由硅 - 锗层形成，第二板由金属形成，并且介电层由五氧化二钽形成。

    Conditioning of dielectric materials
    4.
    发明授权
    Conditioning of dielectric materials 失效
    电介质材料调理

    公开(公告)号：US6090723A

    公开(公告)日：2000-07-18

    申请号：US797900

    申请日：1997-02-10

    申请人： Randhir P. S. Thakur ,  Scott J. Deboer

    发明人： Randhir P. S. Thakur ,  Scott J. Deboer

    IPC分类号： H01L21/3105 ,  H01L21/31

    CPC分类号： H01L21/3105

    摘要： A method for conditioning a dielectric material on a semiconductor substrate structure during a semiconductor fabrication process, comprising the steps of: irradiating the dielectric material using ultraviolet light irradiation while in a ambient exhibiting the properties of self-limiting oxidation, during a first annealing period; following the first annealing period by exposing the dielectric material to an oxygen ambient during a second annealing period. This method may be applied to the conditioning of a capacitor dielectric on a capacitor structure, or to the conditioning of a field effect transistor gate dielectric on a field effect transistor gate structure or to the conditioning of insulative spacers about the sidewalls of a field effect transistor gate structure.

    摘要翻译： 一种用于在半导体制造工艺期间调节半导体衬底结构上的电介质材料的方法，包括以下步骤：在第一退火期间，在显示出自限制氧化性质的环境中，使用紫外光照射照射电介质材料; 在第一退火阶段之后，通过在第二退火阶段期间将电介质材料暴露于氧环境。 该方法可以应用于电容器结构上的电容器电介质的调节，或场效应晶体管栅极结构上的场效应晶体管栅极电介质的调节或者围绕场效应晶体管的侧壁的绝缘隔板的调节 门结构。

    Method and structure for reducing contact aspect ratios
    6.
    发明授权
    Method and structure for reducing contact aspect ratios 有权
    减少接触长宽比的方法和结构

    公开(公告)号：US07268072B2

    公开(公告)日：2007-09-11

    申请号：US11088311

    申请日：2005-03-23

    申请人： Scott J. Deboer ,  Vishnu K. Agarwal

    发明人： Scott J. Deboer ,  Vishnu K. Agarwal

    IPC分类号： H01L21/4763

    CPC分类号： H01L27/10855 ,  H01L21/76895 ,  H01L23/5283 ,  H01L27/10811 ,  H01L27/10888 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An intermediate metal plug is used to raise the platform to which contact is to be made. In the illustrated process, a partial bit line plug is formed adjacent a stacked capacitor, and an interlevel dielectric formed over the capacitor. The bit line contact is completed by extending a via from the bit line, formed above the interlevel dielectric, down to the level of the intermediate plug, and the via is filled with metal. The height of the via to be filled is thus reduced by the height of the intermediate plug. In one embodiment, the intermediate plug is slightly shorter than an adjacent container-shaped capacitor. In another embodiment, the intermediate plug is about as high as an adjacent stud capacitor.

    摘要翻译： 使用中间金属插头来升高要与其接触的平台。 在所示的处理中，在叠层电容器附近形成部分位线插头，在电容器上形成层间电介质。 通过将形成在层间电介质上方的位线延伸到中间插塞的水平面，并且通孔填充金属来完成位线接触。 因此，要填充的通孔的高度被中间塞的高度减小。 在一个实施例中，中间塞略短于相邻的容器状电容器。 在另一个实施例中，中间插头与相邻的插头电容器一样高。

    Method and structure for reducing contact aspect ratios
    8.
    发明授权
    Method and structure for reducing contact aspect ratios 有权
    减少接触长宽比的方法和结构

    公开(公告)号：US06365453B1

    公开(公告)日：2002-04-02

    申请号：US09334842

    申请日：1999-06-16

    申请人： Scott J. Deboer ,  Vishnu K. Agarwal

    发明人： Scott J. Deboer ,  Vishnu K. Agarwal

    IPC分类号： H01L218242

    CPC分类号： H01L27/10855 ,  H01L21/76895 ,  H01L23/5283 ,  H01L27/10811 ,  H01L27/10888 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An intermediate metal plug is used to raise the platform to which contact is to be made. In the illustrated process, a partial bit line plug is formed adjacent a stacked capacitor, and an interlevel dielectric formed over the capacitor. The bit line contact is completed by extending a via from the bit line, formed above the interlevel dielectric, down to the level of the intermediate plug, and the via is filled with metal. The height of the via to be filled is thus reduced by the height of the intermediate plug. In one embodiment, the intermediate plug is slightly shorter than an adjacent container-shaped capacitor. In another embodiment, the intermediate plug is about as high as an adjacent stud capacitor.

    摘要翻译： 使用中间金属插头来升高要与其接触的平台。 在所示的处理中，在叠层电容器附近形成部分位线插头，并在电容器上形成层间电介质。 通过将形成在层间电介质上方的位线延伸到中间插塞的电平，并且通孔填充金属来完成位线接触。 因此，要填充的通孔的高度被中间塞的高度减小。 在一个实施例中，中间塞略短于相邻的容器状电容器。 在另一个实施例中，中间插头与相邻的插头电容器一样高。

    Method and structure for reducing contact aspect ratios
    9.
    发明授权
    Method and structure for reducing contact aspect ratios 失效
    减少接触长宽比的方法和结构

    公开(公告)号：US06878587B2

    公开(公告)日：2005-04-12

    申请号：US10714688

    申请日：2003-11-17

    申请人： Scott J. Deboer ,  Vishnu K. Agarwal

    发明人： Scott J. Deboer ,  Vishnu K. Agarwal

    IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/528 ,  H01L27/108

    CPC分类号： H01L27/10855 ,  H01L21/76895 ,  H01L23/5283 ,  H01L27/10811 ,  H01L27/10888 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An intermediate metal plug is used to raise the platform to which contact is to be made. In the illustrated process, a partial bit line plug is formed adjacent a stacked capacitor, and an interlevel dielectric formed over the capacitor. The bit line contact is completed by extending a via from the bit line, formed above the interlevel dielectric, down to the level of the intermediate plug, and the via is filled with metal. The height of the via to be filled is thus reduced by the height of the intermediate plug. In one embodiment, the intermediate plug is slightly shorter than an adjacent container-shaped capacitor. In another embodiment, the intermediate plug is about as high as an adjacent stud capacitor.

    摘要翻译： 使用中间金属插头来升高要与其接触的平台。 在所示的处理中，在叠层电容器附近形成部分位线插头，在电容器上形成层间电介质。 通过将形成在层间电介质上方的位线延伸到中间插塞的电平，并且通孔填充金属来完成位线接触。 因此，要填充的通孔的高度被中间塞的高度减小。 在一个实施例中，中间塞略短于相邻的容器状电容器。 在另一个实施例中，中间插头与相邻的插头电容器一样高。