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公开(公告)号：US20050060365A1
公开(公告)日：2005-03-17
申请号：US10057163
申请日：2002-01-24
申请人： Scott Robinson , Uttam Sengupta , Andrew Anderson , Steven Bennett , Paul Pierce , Trevor Pering , Nicholas Wade , Shreekant Thakkar , Kit Tham
发明人： Scott Robinson , Uttam Sengupta , Andrew Anderson , Steven Bennett , Paul Pierce , Trevor Pering , Nicholas Wade , Shreekant Thakkar , Kit Tham
CPC分类号： H04L67/322 , H04L69/329
摘要： Methods and apparatus are provided for processing information items. Processing comprises one of context filtering, context prioritizing, or both context filtering and context prioritizing. In some embodiments the set of context items from which processing criteria are derived includes a user's calendar of appointments, schedule changes, exceptions, and the like.
摘要翻译： 提供了处理信息项的方法和装置。 处理包括上下文过滤，上下文优先级或上下文过滤和上下文优先级之一。 在一些实施例中，来自处理标准的上下文项目的集合包括用户的约会日历，日程表更改，例外等。
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2.发明授权Method and apparatus for providing deterministic read access to main memory in a computer system 失效用于在计算机系统中提供对主存储器的确定性读取访问的方法和装置
公开(公告)号：US5613075A
公开(公告)日：1997-03-18
申请号：US585598
申请日：1996-01-12
申请人： Nicholas Wade , Mark Lalich , Bruce Young
发明人： Nicholas Wade , Mark Lalich , Bruce Young
CPC分类号： G06F13/1673 , G06F13/4027
摘要： A method for guaranteeing access to a bus master for reads of main memory in a bridge circuit for joining a host processor, main memory, and a PCI bus, by detecting a read with data posted in the posted write buffer, disabling the posted write buffer, disabling access by the host processor for a selected period, detecting the presence of a retry of the read access, and enabling the posted write buffer after detecting an idle bus for the passage of the preselected time.
摘要翻译： 一种用于通过检测利用发布在写入缓冲器中的数据进行读取来保证访问总线主机以访问用于连接主处理器，主存储器和PCI总线的桥接电路中的主存储器的方法，禁用发布的写入缓冲器 ，禁止所述主机处理器访问所选择的周期，检测所述读取访问的重试的存在，以及在检测到空闲总线以通过所述预选时间之后启用所述发布的写入缓冲器。
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3.发明授权Method and apparatus for dynamically resizing a frame buffer in a shared memory buffer architecture system 有权用于在共享存储器缓冲器架构系统中动态地调整帧缓冲器大小的方法和装置
公开(公告)号：US5953746A
公开(公告)日：1999-09-14
申请号：US217946
申请日：1998-12-21
CPC分类号： G06F12/0223 , G09G2360/125 , G09G5/39
摘要： A method and system for dynamically sizing a dedicated memory in a shared memory buffer architecture. At initial boot, system BIOS programs control register to allocate a dedicated memory of a desired size. The size of the dedicated memory allocated is dependent on the performance requirements. If after initial boot, the performance requirements change, it may necessitate a change in dedicated memory size. By reprogramming the control registers, the dedicated memory size is dynamically changed without any manual manipulation of internal components.
摘要翻译： 一种用于在共享存储器缓冲器架构中动态地调整专用存储器的尺寸的方法和系统。 在初始启动时，系统BIOS程序控制寄存器以分配所需大小的专用存储器。 分配的专用内存的大小取决于性能要求。 如果在初始引导后，性能要求发生变化，则可能需要更改专用内存大小。 通过重新编程控制寄存器，专门的存储器大小是动态变化的，无需任何手动操作内部组件。
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4.发明授权Method and apparatus for dynamically allocating and resizing the dedicated memory in a shared memory buffer architecture system 失效用于在共享存储器缓冲器架构系统中动态地分配和调整专用存储器大小的方法和装置
公开(公告)号：US5915265A
公开(公告)日：1999-06-22
申请号：US577490
申请日：1995-12-22
CPC分类号： G06F12/0223 , G09G2360/125 , G09G5/39
摘要： A method and system for dynamically sizing a dedicated memory in a shared memory buffer architecture. At initial boot, system BIOS programs control register to allocate a dedicated memory of a desired size. The size of the dedicated memory allocated is dependent on the performance requirements. If after initial boot, the performance requirements change, it may necessitate a change in dedicated memory size. By reprogramming the control registers, the dedicated memory size is dynamically changed without any manual manipulation of internal components.
摘要翻译： 一种用于在共享存储器缓冲器架构中动态地调整专用存储器的尺寸的方法和系统。 在初始启动时，系统BIOS程序控制寄存器以分配所需大小的专用存储器。 分配的专用内存的大小取决于性能要求。 如果在初始引导后，性能要求发生变化，则可能需要更改专用内存大小。 通过重新编程控制寄存器，专门的存储器大小是动态变化的，无需任何手动操作内部组件。
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5.发明授权Method and apparatus to permit the boot of a shared memory buffer architecture employing an arbitrary operating system 失效允许引导使用任意操作系统的共享存储器缓冲器架构的方法和装置
公开(公告)号：US5790849A
公开(公告)日：1998-08-04
申请号：US587775
申请日：1995-12-22
CPC分类号： G06F9/5016 , G06F12/0684 , G06F9/4411
摘要： A method and system for allowing an arbitrary operating boot in a shared memory buffer architecture system. A chipset including a memory controller, a bridge, and an arbitration unit is used to control access to a shared physical memory. The physical memory is divided between the system memory and dedicated memory to be used by one or more devices. A portion of the physical memory is allocated as a dedicated memory for some system device. The remainder of the memory may be allocated as system memory. The allocation is performed by a system BIOS either at initial start up or through system BIOS calls made during initialization of the device to use the dedicated memory. Programmable bits in the chipset are programmed to prevent the memory controller from claiming dedicated memory accesses during the boot of an operating system. Since the operating system's attempts to write to the dedicated memory are not claimed by the memory controller during memory sizing, they are forwarded to an I/O bus. No 1/0 device claims these addresses, so a memory sizing read back is unanswered, and the operating system is caused to believe the top of memory has been reached below the dedicated memory. If the O/S does not do memory sizing, the system BIOS provides the O/S with the size of system memory available. Thus, in either case, the dedicated memory allocation is transparent to the O/S, and an arbitrary O/S may be employed with the system.
摘要翻译： 一种用于在共享存储器缓冲器架构系统中允许任意操作引导的方法和系统。 使用包括存储器控制器，桥接器和仲裁单元的芯片组来控制对共享物理存储器的访问。 物理存储器被划分在系统存储器和专用存储器之间以被一个或多个设备使用。 物理存储器的一部分被分配为用于某些系统设备的专用存储器。 存储器的其余部分可以被分配为系统存储器。 分配由系统BIOS执行，在初始启动时或通过在设备初始化期间进行的系统BIOS调用来使用专用存储器。 芯片组中的可编程位被编程以防止存储器控制器在操作系统引导期间声称专用存储器访问。 由于操作系统写入专用存储器的尝试在存储器大小调整期间不被存储器控制器要求，所以它们被转发到I / O总线。 没有1/0设备声称这些地址，所以回读的内存大小调整未被回答，并且操作系统导致相信内存的顶部已经达到专用内存以下。 如果O / S没有进行内存大小调整，系统BIOS会为系统内存的大小提供O / S。 因此，在任一情况下，专用存储器分配对于O / S是透明的，并且可以在系统中使用任意的O / S。
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公开(公告)号：US5155843A
公开(公告)日：1992-10-13
申请号：US547597
申请日：1990-06-29
申请人： Rebecca L. Stamm , R. Iris Bahar , Michael Callander , Linda Chao , Derrick R. Meyer , Douglas Sanders , Richard L. Sites , Raymond Strouble , Nicholas Wade
发明人： Rebecca L. Stamm , R. Iris Bahar , Michael Callander , Linda Chao , Derrick R. Meyer , Douglas Sanders , Richard L. Sites , Raymond Strouble , Nicholas Wade
CPC分类号： G06F12/0804 , G06F12/0815 , F02B2075/025
摘要： A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. Macroinstruction pipelining is employed (instead of microinstruction pipelining), with queueing between units of the CPU to allow flexibility in instruction execution times. A wide bandwidth is available for memory access; fetching 64-bit data blocks on each cycle. A hierarchical cache arrangement has an improved method of cache set selection, increasing the likelihood of a cache hit. A writeback cache is used (instead of writethrough) and writeback is allowed to proceed even though other accesses are suppressed due to queues being full. A branch prediction method employs a branch history table which records the taken vs. not-taken history of branch opcodes recently used, and uses an empirical algorithm to predict which way the next occurrence of this branch will go, based upon the history table. A floating point processor function is integrated on-chip, with enhanced speed due to a bypass technique; a trial mini-rounding is done on low-order bits of the result, and if correct, the last stage of the floating point processor can be bypassed, saving one cycle of latency. For CAL type instructions, a method for determining which registers need to be saved is executed in a minimum number of cycles, examining groups of register mask bits at one time. Internal processor registers are accessed with short (byte width) addresses instead of full physical addresses as used for memory and I/O references, but off-chip processor registers are memory-mapped and accessed by the same busses using the same controls as the memory and I/O. In a non-recoverable error detected by ECC circuits in the cache, an error transition mode is entered wherein the cache operates under limited access rules, allowing a maximum of access by the system for data blocks owned by the cache, but yet minimizing changes to the cache data so that diagnostics may be run. Separate queues are provided for the return data from memory and cache invalidates, yet the order or bus transactions is maintained by a pointer arrangement. The bus protocol used by the CPU to communicate with the system bus is of the pended type, with transactions on the bus identified by an ID field specifying the originator, and arbitration for bus grant goes one simultaneously with address/data transactions on the bus.
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