公开(公告)号：US20130105784A1

公开(公告)日：2013-05-02

申请号：US13722028

申请日：2012-12-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Ryota IMAHAYASHI ,  Shinobu FURUKAWA ,  Atsuo ISOBE ,  Yasuyuki ARAI ,  Shunpei YAMAZAKI

IPC: H01L51/05 ,  H01L51/00

CPC classification number: H01L51/0512 ,  H01L21/02175 ,  H01L21/02244 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/31683 ,  H01L51/0002 ,  H01L51/0055 ,  H01L51/0525 ,  H01L51/0541 ,  H01L51/0545 ,  H01L51/0566

Abstract: It is an object to form a high quality gate insulating film which is dense and has a strong insulation resistance property, and to propose a high reliable organic transistor in which a tunnel leakage current is little. One mode of the organic transistor of the present invention has a step of forming the gate insulating film by forming the conductive layer which becomes the gate electrode activating oxygen (or gas including oxygen) or nitrogen (or gas including nitrogen) or the like using dense plasma in which density of electron is 1011 cm−3 or more, and electron temperature is a range of 0.2 eV to 2.0 eV with plasma activation, and reacting directly with a portion of the conductive layer which becomes the gate electrode to be insulated.

Abstract translation: 本发明的目的是形成致密且具有很强绝缘电阻特性的高质量栅极绝缘膜，并且提出了隧道泄漏电流很小的高可靠性有机晶体管。 本发明的有机晶体管的一种模式具有如下步骤：通过使用密集的方法形成作为活化氧（或含氧气体）或氮（或含氮气体）的栅极的导电层形成栅极绝缘膜 电子密度为1011cm -3以上的等离子体，等离子体活化时电子温度为0.2eV〜2.0eV的范围，直接与成为要被绝缘的栅电极的导体层的一部分反应。

公开(公告)号：US20140151692A1

公开(公告)日：2014-06-05

申请号：US14172072

申请日：2014-02-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiromichi GODO ,  Ryota IMAHAYASHI ,  Kiyoshi KATO

IPC: H01L29/786 ,  H01L29/66

Abstract: Disclosed is a semiconductor device including: an insulating layer; a source electrode and a drain electrode embedded in the insulating layer; an oxide semiconductor layer in contact and over the insulating layer, the source electrode, and the drain electrode; a gate insulating layer over and covering the oxide semiconductor layer; and a gate electrode over the gate insulating layer, where the upper surfaces of the insulating layer, the source electrode, and the drain electrode exist coplanarly. The upper surface of the insulating layer, which is in contact with the oxide semiconductor layer, has a root-mean-square (RMS) roughness of 1 nm or less, and the difference in height between the upper surface of the insulating layer and the upper surface of the source electrode or the drain electrode is less than 5 nm. This structure contributes to the suppression of defects of the semiconductor device and enables their miniaturization.

Abstract translation: 公开了一种半导体器件，包括：绝缘层; 源极电极和漏电极，嵌入绝缘层中; 与所述绝缘层，所述源极电极和所述漏电极接触的氧化物半导体层; 覆盖氧化物半导体层的栅极绝缘层; 以及栅极绝缘层上的栅电极，其中绝缘层，源电极和漏电极的上表面共面存在。 与氧化物半导体层接触的绝缘层的上表面的均方根（RMS）粗糙度为1nm以下，绝缘层的上表面与 源电极或漏电极的上表面小于5nm。 这种结构有助于抑制半导体器件的缺陷并使其能够小型化。